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Machine translation
1. (WO2000029919) RAPID ON CHIP VOLTAGE GENERATION FOR LOW POWER INTEGRATED CIRCUITS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2000/029919    International Application No.:    PCT/US1998/024766
Publication Date: 25.05.2000 International Filing Date: 18.11.1998
Chapter 2 Demand Filed:    16.06.2000    
IPC:
B60K 20/00 (2006.01), C08G 59/06 (2006.01), F02M 61/10 (2006.01), G05F 1/10 (2006.01), G05F 1/46 (2006.01), G05F 3/02 (2006.01), G05F 3/20 (2006.01), G11C 5/14 (2006.01), G11C 11/413 (2006.01), G11C 16/06 (2006.01), H01L 21/822 (2006.01), H01L 27/02 (2006.01), H01L 27/04 (2006.01)
Applicants: MACRONIX INTERNATIONAL CO., LTD. [--/--]; 3 Creation Road 3rd. Science-Based Industrial Park Hsinchu Taiwan 300 (TW) (For All Designated States Except US).
CHANG, Kuen-Long [--/--]; (TW) (For US Only).
HUNG, Chun-Hsiung [--/--]; (TW) (For US Only).
CHEN, Ken-Hui [--/--]; (TW) (For US Only).
HO, Tien-Shin [--/--]; (TW) (For US Only).
LEE, I-Long [--/--]; (TW) (For US Only).
SHIAU, Tzeng-Hei [--/--]; (TW) (For US Only).
WAN, Ray-Lin [US/US]; (US) (For US Only)
Inventors: CHANG, Kuen-Long; (TW).
HUNG, Chun-Hsiung; (TW).
CHEN, Ken-Hui; (TW).
HO, Tien-Shin; (TW).
LEE, I-Long; (TW).
SHIAU, Tzeng-Hei; (TW).
WAN, Ray-Lin; (US)
Agent: HAYNES, Mark, A.; Wilson Sonsini Goodrich & Rosati 650 Page Mill Road Palo Alto, CA 94304-1050 (US)
Priority Data:
Title (EN) RAPID ON CHIP VOLTAGE GENERATION FOR LOW POWER INTEGRATED CIRCUITS
(FR) GENERATION RAPIDE DE TENSION DANS LE MICROCIRCUIT DANS LE CAS DE CIRCUITS INTEGRES COURANT FAIBLE
Abstract: front page image
(EN)An on chip voltage generation circuit is provided for use on integrated circuits such as flash memory devices with a low power supply voltage. The voltage generation circuit comprises first and second level detectors (209 and 210) and a boost driver (204), wherein the voltage generation circuit pumps charge at first and second rates in response to outputs of the detectors.
(FR)L'invention concerne un circuit générateur de tension dans le microcircuit destiné aux circuits intégrés tels que des mémoires flash à tension d'alimentation basse. Le circuit générateur de tension comprend un premier et un second détecteur de niveau (209, 210) et un circuit d'attaque de tension d'appoint (204). Le circuit générateur de tension pompe la charge à un premier et à un second débit en réponse aux sorties des détecteurs.
Designated States: CN, JP, US.
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE).
Publication Language: English (EN)
Filing Language: English (EN)