Feedback
Settings

Settings

Goto Application

1. WO2000027031 - FLIP-FLOP CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

PermaLink
Publication Number WO/2000/027031
Publication Date 11.05.2000
International Application No. PCT/JP1998/004923
International Filing Date 30.10.1998
Chapter 2 Demand Filed 30.10.1998
IPC
H03K 3/356 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
3Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02Generators characterised by the type of circuit or by the means used for producing pulses
353by the use, as active elements, of field-effect transistors with internal or external positive feedback
356Bistable circuits
CPC
H03K 3/356139
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
3Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02Generators characterised by the type of circuit or by the means used for producing pulses
353by the use, as active elements, of field-effect transistors with internal or external positive feedback
356Bistable circuits
356104using complementary field-effect transistors
356113using additional transistors in the input circuit
35613the input circuit having a differential configuration
356139with synchronous operation
Applicants
  • HITACHI, LTD. [JP]/[JP] (AllExceptUS)
  • TANIMOTO, Tadaaki [JP]/[JP] (UsOnly)
Inventors
  • TANIMOTO, Tadaaki
Agents
  • OBINATA, Tomio
Priority Data
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) FLIP-FLOP CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
(FR) BASCULE ET CIRCUIT INTEGRE A SEMI-CONDUCTEURS
front page image
Abstract
(EN)
A flip-flop circuit having a logic circuit between a master latch circuit and a slave latch circuit. A transmission MOS transistor is used instead of a logic gate circuit as a means constituting the logic circuit and the transmission MOS transistor as a MOS transistor which constitutes the slave latch circuit and is operated by clock signals.
(FR)
L'invention concerne une bascule, possédant un circuit logique placé entre un circuit de verrouillage maître et un circuit de verrouillage asservi. On utilise un transistor de transmission MOS à lieu d'un circuit à grille logique comme organe constituant le circuit logique, et le transistor de transmission MOS comme transistor MOS constituant le circuit de verrouillage asservi, et fonctionnant à l'aide de signaux d'horloge.
Also published as
AU1998096509
JPWO2000027031
Latest bibliographic data on file with the International Bureau
# -