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Machine translation
1. (WO2000026920) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2000/026920    International Application No.:    PCT/JP1998/004902
Publication Date: 11.05.2000 International Filing Date: 29.10.1998
Chapter 2 Demand Filed:    29.10.1998    
IPC:
G11C 5/02 (2006.01), G11C 11/419 (2006.01)
Applicants: HITACHI, LTD. [JP/JP]; 6, Kanda Surugadai 4-chome Chiyoda-ku Tokyo 101-8010 (JP) (For All Designated States Except US).
HITACHI ULSI SYSTEMS CO., LTD. [JP/JP]; 22-1, Josuihoncho 5-chome Kodaira-shi Tokyo 187-8522 (JP) (For All Designated States Except US).
ENDO, Hitoshi [JP/JP]; (JP) (For US Only).
WAKASUGI, Katsuhiko [JP/JP]; (JP) (For US Only).
SATO, Youichi [JP/JP]; (JP) (For US Only).
SATO, Kazuyoshi [JP/JP]; (JP) (For US Only)
Inventors: ENDO, Hitoshi; (JP).
WAKASUGI, Katsuhiko; (JP).
SATO, Youichi; (JP).
SATO, Kazuyoshi; (JP)
Agent: TOKUWAKA, Kousei; 16-8, Inokashira 5-chome Mitaka-shi Tokyo 181-0001 (JP)
Priority Data:
Title (EN) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
(FR) DISPOSITIF DE CIRCUIT INTEGRE SEMI-CONDUCTEUR
Abstract: front page image
(EN)A memory cell array comprising static memory cells, wherein preamplifiers which receive the signals of the memory cells read out on complementary bit line pairs and main amplifiers which receive the output signals of the preamplifiers are provided. The number of the memory cells connected to the complementary bit lines is limited so that the amplitudes of the signals which are supplied to the inputs of the preamplifier and read out on the bit line pairs may be larger than those of the output signals of the preamplifiers.
(FR)La présente invention concerne un réseau de cellules mémoire comprenant des cellules de mémoire statique, dans lequel des préamplificateurs reçoivent les signaux des cellules mémoire lus sur des paires de lignes de bits complémentaires, et des amplificateurs principaux reçoivent les signaux de sortie des préamplificateurs. Le nombre de cellules mémoires reliées aux lignes de bits complémentaires est limité de manière à ce que les amplitudes des signaux fournis aux entrées du préamplificateur et lus sur les paires de lignes de bits puissent être plus grandes que celles des signaux de sortie des préamplificateurs.
Designated States: CN, JP, KR, SG, US.
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)