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1. WO1999060479 - SINGLE AND MULTIPLE CHANNEL MEMORY DETECTION AND SIZING

Publication Number WO/1999/060479
Publication Date 25.11.1999
International Application No. PCT/US1999/004720
International Filing Date 03.03.1999
Chapter 2 Demand Filed 22.11.1999
IPC
G06F 12/00 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
CPC
G06F 12/0684
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
0646Configuration or reconfiguration
0684with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
G06F 13/1694
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1668Details of memory controller
1694Configuration of memory controller to different memory types
G11C 11/4072
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4072Circuits for initialisation, powering up or down, clearing memory or presetting
G11C 7/20
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
20Memory initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
Applicants
  • INTEL CORPORATION [US]/[US] (AllExceptUS)
  • WIRT, Lynda, M. [US]/[US] (UsOnly)
Inventors
  • WIRT, Lynda, M.
Agents
  • TAYLOR, Edwin, H.
Priority Data
09/080,87218.05.1998US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SINGLE AND MULTIPLE CHANNEL MEMORY DETECTION AND SIZING
(FR) DETECTION ET DIMENSIONNEMENT DE LA MEMOIRE A CANAL UNIQUE OU MULTIPLE
Abstract
(EN)
As shown in Figures 4, 5, 6 and 7, a method for BIOS code for detecting and grouping memory devices connected to one or more memory channels, comprising reading characteristics of a memory device (414) and if the characteristics have not been previously read, then programming device ID and group ID registers based upon a device counter and a group counter, respectively (422). The method further includes steps for properly incrementing the device and group counters so that additional memory devices on the channel may be read and grouped.
(FR)
L'invention concerne un procédé, illustré dans les figures 4, 5, 6 et 7, de détection et de regroupement de mémoires connectées à un ou plusieurs canal(aux) de mémoire pour le code BIOS. Ce procédé consiste à lire les caractéristiques d'une mémoire (414) et si ces caractéristiques n'ont pas encore été lues, à programmer l'identification de la mémoire et les registres d'identification du groupe selon un compteur de mémoire et un compteur de groupe respectivement (422). Ce procédé consiste aussi à augmenter correctement les compteurs de mémoire et de groupe de manière à permettre la lecture et le regroupement des mémoires supplémentaires sur le canal.
Also published as
DE19983256
GBGB0027775.6
Latest bibliographic data on file with the International Bureau