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1. WO1999059288 - A METHOD AND APPARATUS FOR HARDWARE BLOCK LOCKING IN A NONVOLATILE MEMORY

Publication Number WO/1999/059288
Publication Date 18.11.1999
International Application No. PCT/US1999/009462
International Filing Date 30.04.1999
Chapter 2 Demand Filed 19.11.1999
IPC
G06F 12/14 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
14Protection against unauthorised use of memory
G11C 16/22 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
22Safety or protection circuits preventing unauthorised or accidental access to memory cells
CPC
G06F 12/1433
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
14Protection against unauthorised use of memory ; or access to memory
1416by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
1425the protection being physical, e.g. cell, word, block
1433for a module or a part of a module
G11C 16/22
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
22Safety or protection circuits preventing unauthorised or accidental access to memory cells
Applicants
  • INTEL CORPORATION [US]/[US] (AllExceptUS)
  • GAFKEN, Andrew, H. [US]/[US] (UsOnly)
Inventors
  • GAFKEN, Andrew, H.
Agents
  • TAYLOR, Edwin, H.
Priority Data
09/078,09411.05.1998US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) A METHOD AND APPARATUS FOR HARDWARE BLOCK LOCKING IN A NONVOLATILE MEMORY
(FR) PROCEDE ET APPAREIL DE BLOCAGE D'UN BLOC MATERIEL D'UNE MEMOIRE NON VOLATILE
Abstract
(EN)
The memory device (200) includes a nonvolatile memory array (215) including a first block of memory cells (230). The first volatile protection bit coupled to the first block is programmable to prevent a memory access operation directed to the first block from being performed.
(FR)
L'invention porte sur un dispositif de mémoire (200) comportant un réseau de mémoires non volatiles (215) comportant un premier bloc de cellules (230) de mémoire. Le premier bit volatile de protection relié au premier bloc est programmable pour empêcher une opération d'accès à la mémoire dirigée sur le premier bloc.
Also published as
GBGB0027059.5
Latest bibliographic data on file with the International Bureau