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1. WO1999030325 - SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS USING THE SEMICONDUCTOR DEVICE

Publication Number WO/1999/030325
Publication Date 17.06.1999
International Application No. PCT/JP1998/005587
International Filing Date 10.12.1998
IPC
G11C 11/4074 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
CPC
G11C 11/404
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
403with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
404with one charge-transfer gate, e.g. MOS transistor, per cell
G11C 11/4074
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
Applicants
  • SEIKO EPSON CORPORATION [JP]/[JP] (AllExceptUS)
  • MARUYAMA, Akira [JP]/[JP] (UsOnly)
Inventors
  • MARUYAMA, Akira
Agents
  • INOUE, Hajime
Priority Data
9/34108811.12.1997JP
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS USING THE SEMICONDUCTOR DEVICE
(FR) MEMOIRE A SEMICONDUCTEURS, DISPOSITIF A SEMICONDUCTEURS ET APPAREIL ELECTRONIQUE UTILISANT LEDIT DISPOSITIF A SEMICONDUCTEURS
Abstract
(EN) A memory cell (1) is provided with a MOS transistor (5) and a data holding capacitor (7). One of the two input-output electrodes of the transistor (5) is connected to a bit line (36) and the gate electrode of the transistor (5) is connected to a word line (37). The first electrode (6) of the capacitor (7) is connected to the other input-output electrode of the transistor (5), and the second electrode (14) is connected to a potential control circuit (40). When the data held in the memory cell (5) is HIGH, the potential control circuit (40) changes the potential at the second electrode (14) to a ground potential GND from a precharge potential VCC/2 after the write/read of the data held in the memory cell (1). When the data held in the memory cell (5) is LOW, the circuit (40) changes the potential at the second electrode (14) to a power supply potential VCC from the precharge potential VCC/2 after the write/read of the data.
(FR) L'invention concerne une cellule mémoire (1) pourvue d'un transistor MOS (5) et d'un condensateur (7) mémoire de données. L'une des deux électrodes d'entrée-sortie du transistor (5) est reliée à une ligne (36) de bits, l'électrode de commande du transistor (5) étant relié à une ligne (37) de mots. La première électrode (6) du condensateur (7) est reliée à l'autre électrode d'entrée-sortie du transistor (5), la deuxième électrode (14) étant reliée à un circuit (40) de commande de potentiel. Lorsque les données renfermées dans la cellule mémoire (5) déterminent un niveau haut, le circuit (40) de commande de potentiel fait passer le potentiel de la deuxième électrode (14) d'un potentiel de précharge (VCC/2) à un potentiel de masse (GND), en réaction à l'écriture/lecture des données renfermées dans la cellule mémoire (1). Lorsque les données renfermées dans la cellule mémoire (5) déterminent un niveau bas, après écriture/lecture des données, le circuit (40) fait passer le potentiel de la deuxième électrode (14) d'un potentiel de précharge (VCC/2) à un potentiel d'alimentation électrique (VCC).
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