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1. (WO1999013475) LOW COST, HIGHLY PARALLEL MEMORY TESTER

Pub. No.:    WO/1999/013475    International Application No.:    PCT/US1998/018602
Publication Date: Mar 18, 1999 International Filing Date: Sep 4, 1998
IPC: G01R 31/319
G11C 29/56
Applicants: TERADYNE, INC.
Inventors: CONNER, George, W.
Title: LOW COST, HIGHLY PARALLEL MEMORY TESTER
Abstract:
Automatic test equipment for semiconductor memories that provides testing of large arrays of semiconductor memory chips in parallel. Such massively parallel memory testing greatly enhances test throughput, thereby reducing cost. It greatly enhances the economics of testing memory device made according to a RAMBUS standard, which includes a low speed port and a medium speed port because it allows the same automatic test equipment to economically be used to test devices with the low speed port and the medium speed port.