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1. (WO1999010982) CURRENT CONTROL TECHNIQUE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/1999/010982 International Application No.: PCT/US1998/017942
Publication Date: 04.03.1999 International Filing Date: 27.08.1998
IPC:
G06F 13/40 (2006.01) ,G11C 7/10 (2006.01) ,H03K 19/003 (2006.01) ,H04L 25/02 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38
Information transfer, e.g. on bus
40
Bus structure
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
10
Input/output (I/O) data interface arrangements, e.g. I/O data control circuits, I/O data buffers
[IPC code unknown for H03K 19/03]
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
25
Baseband systems
02
Details
Applicants:
RAMBUS INCORPORATED [US/US]; 2465 Latham Street Mountain View, CA 94040, US
Inventors:
GARRETT, Billy, Wayne, Jr.; US
DILLON, John, B.; US
CHING, Michael, Tak-Kei; US
STONECYPHER, William, F.; US
CHAN, Andy, Peng-Pui; US
GRIFFIN, Matthew, M.; US
Agent:
GALLIANI, William, S. ; Flehr Hohbach Test Albritton & Herbert LLP Suite 3400 4 Embarcadero Center San Francisco, CA 94111-4187, US
Priority Data:
60/057,40029.08.1997US
60/073,35302.02.1998US
Title (EN) CURRENT CONTROL TECHNIQUE
(FR) TECHNIQUE DE COMMANDE DE COURANT
Abstract:
(EN) An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).
(FR) L'invention concerne un circuit amplificateur de commande de sortie et une technique de commande de courant permettant d'activer des bus à grande vitesse et à faible bruit, qui sont utilisés avec des mémoires RAM dynamiques à grande vitesse (DRAM). L'architecture comporte les éléments suivants: un bloc (120) d'isolation d'entrée, un diviseur (104) analogique de tension, un comparateur (125) d'entrée, un verrou (130) d'échantillonnage, un compteur (115) de courant de commande et un amplificateur de commande de sortie au niveau des bits (amplificateurs de commande de sortie A 107 et B 111).
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Designated States: CA, JP, KR
European Patent Office (EPO) (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)