Search International and National Patent Collections

1. (WO1999009599) VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH DIELECTRIC ISOLATION

Pub. No.:    WO/1999/009599    International Application No.:    PCT/US1998/016900
Publication Date: Feb 25, 1999 International Filing Date: Aug 14, 1998
IPC: H01L 21/98
Applicants: CUBIC MEMORY, INC.
Inventors: VINDASIUS, Alfons
SAUTTER, Kenneth, M.
Title: VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH DIELECTRIC ISOLATION
Abstract:
An apparatus vertically interconnects stacks of silicon segments (36). Each segment (36) includes a plurality of adjacent die on a semiconductor wafer (30). The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads (42) for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls (102) on each of the segments (36). After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack. The inwardly sloping edge walls of each of the segments in the stack provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked. A dielectric coating is applied to the die to provide a conformal coating to protect and insulate the die and a laser is used to ablate the area over the bond pads to remove the dielectric coating in order to provide for electrical connections to bond pads.