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1. WO1999008285 - METHOD FOR PREVENTING SUB-THRESHOLD LEAKAGE IN FLASH MEMORY CELLS

Publication Number WO/1999/008285
Publication Date 18.02.1999
International Application No. PCT/US1998/016297
International Filing Date 05.08.1998
IPC
G11C 11/56 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
56using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
G11C 16/34 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
CPC
G11C 11/5621
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
56using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
5621using charge storage in a floating gate
G11C 11/5628
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
56using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
5621using charge storage in a floating gate
5628Programming or writing circuits; Data input circuits
G11C 11/5635
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
56using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
5621using charge storage in a floating gate
5628Programming or writing circuits; Data input circuits
5635Erasing circuits
G11C 11/5642
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
56using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
5621using charge storage in a floating gate
5642Sensing or reading circuits; Data output circuits
G11C 16/0416
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
0408comprising cells containing floating gate transistors
0416comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
G11C 16/34
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
Applicants
  • APLUS FLASH TECHNOLOGY, INC. [US]/[US]
Inventors
  • LEE, Peter, W.
  • HSU, Fu-Chang
  • TSAO, Hsing-Ya
Agents
  • JAKOPIN, David, A.
Priority Data
08/906,19805.08.1997US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) METHOD FOR PREVENTING SUB-THRESHOLD LEAKAGE IN FLASH MEMORY CELLS
(FR) PROCEDE SERVANT A EMPECHER UNE FUITE PAR COURANT INFRASEUIL DANS DES CELLULES A MEMOIRE FLASH
Abstract
(EN) The present invention provides a method for preventing sub-threshold leakage in flash EPROM cells (M102, M104, M106, M108) during Vt repair, read and verify operations. The present invention prevents sub-threshold leakage by either biasing the floating gate voltage of non-selected cells to a level that is less than the sources voltage. This biasing is achieved by controlling the voltages applied to such non-selected cells bitline and wordline voltages, or by floating the non-selected sourcelines to electrically disconnect the sourcelines of the non-selected cells. This method allows fast and accurate Vt repair of cells while avoiding Vt degradation of non-erased and repaired cells due to sub-threshold current leakage, as well as reduced sub-threshold leakage during read and verify operations.
(FR) La présente invention concerne un procédé servant à empêcher une fuite par courant infraseuil, dans des cellules à mémoire flash (M102, M104, M106, M108), lors d'opérations de réparation de la tension, de lecture et de vérification, et elle permet d'empêcher une fuite par courant infraseuil, notamment par polarisation de la tension de la grille flottante des cellules non choisies, afin de porter cette tension à un niveau inférieur à celui de la tension de la source. On exécute cette polarisation en régulant les tensions appliquées à des tensions de ligne de mots et de ligne de binaire de cellules non choisies, ou par flottement des lignes sources non choisies, afin de déconnecter électriquement les lignes sources des cellules non choisies. Ce procédé permet de réparer rapidement et précisément la tension des cellules et d'éviter en même temps une dégradation de la tension de seuil des cellules réparées et non effacées, provoquée par une fuite par courant infraseuil, de même que la fuite réduite par courant infraseuil, lors d'opérations de lecture et de vérification.
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