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1. WO1999008191 - TRANSLATED MEMORY PROTECTION APPARATUS FOR AN ADVANCED MICROPROCESSOR

Publication Number WO/1999/008191
Publication Date 18.02.1999
International Application No. PCT/US1997/014117
International Filing Date 11.08.1997
Chapter 2 Demand Filed 25.11.1998
IPC
G06F 9/38 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
G06F 9/455 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
44Arrangements for executing specific programs
455Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 12/14 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
14Protection against unauthorised use of memory
CPC
G06F 12/14
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
14Protection against unauthorised use of memory ; or access to memory
G06F 12/145
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
14Protection against unauthorised use of memory ; or access to memory
1416by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
145the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
G06F 9/3812
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3802Instruction prefetching
3812with instruction modification, e.g. store into instruction stream
G06F 9/45504
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
44Arrangements for executing specific programs
455Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
45504Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
Applicants
  • TRANSMETA CORPORATION [US]/[US]
Inventors
  • KELLY, Edmund, J.
  • CMELIK, Robert, F.
  • WING, Malcolm, J.
Agents
  • KING, Stephen, L.
Priority Data
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) TRANSLATED MEMORY PROTECTION APPARATUS FOR AN ADVANCED MICROPROCESSOR
(FR) DISPOSITIF DE PROTECTION DE MEMOIRE D'INSTRUCTIONS TRADUITES POUR MICROPROCESSEUR EVOLUE
Abstract
(EN) A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.
(FR) L'invention traite d'un procédé permettant de répondre à une tentative d'écriture au niveau d'une adresse en mémoire comportant une instruction cible qui a été traduite en instruction hôte en vue de son exécution par un processeur hôte. Ce procédé consiste à marquer une adresse en mémoire comportant une instruction cible qui a été traduite en instruction hôte; à déceler une adresse en mémoire qui a été marquée lors d'une tentative d'écriture au niveau de cette adresse en mémoire; et à répondre à la détection d'une adresse en mémoire marquée en protégeant une instruction cible située au niveau de l'adresse en mémoire jusqu'à ce qu'il soit certain que les traductions associées à ladite adresse en mémoire ne seront pas utilisées avant d'avoir été mises à jour.
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