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1. (WO1998053489) INTEGRATED CIRCUIT, COMPONENTS THEREOF AND MANUFACTURING METHOD
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1998/053489 International Application No.: PCT/SE1998/000929
Publication Date: 26.11.1998 International Filing Date: 18.05.1998
Chapter 2 Demand Filed: 11.12.1998
IPC:
H01L 21/265 (2006.01) ,H01L 21/331 (2006.01) ,H01L 21/762 (2006.01) ,H01L 21/763 (2006.01) ,H01L 29/08 (2006.01) ,H01L 29/417 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
26
Bombardment with wave or particle radiation
263
with high-energy radiation
265
producing ion implantation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
328
Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors
33
the devices comprising three or more electrodes
331
Transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
762
Dielectric regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
763
Polycrystalline semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
08
with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
417
carrying the current to be rectified, amplified or switched
Applicants:
TELEFONAKTIEBOLAGET LM ERICSSON [SE/SE]; S-126 25 Stockholm, SE
Inventors:
NORSTRÖM, Hans, Erik; SE
HONG, Sam-Hyo; SE
LINDGREN, Bo, Anders; SE
LARSSON, Torbjörn; SE
Agent:
ERICSSON COMPONENTS AB; Dept. for Intellectual Property Rights S-164 81 Stockholm, SE
Priority Data:
9701934-323.05.1997SE
Title (EN) INTEGRATED CIRCUIT, COMPONENTS THEREOF AND MANUFACTURING METHOD
(FR) CIRCUIT INTEGRE, COMPOSANTS DE CE CIRCUIT ET PROCEDE DE PRODUCTION
Abstract:
(EN) The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or made amorphous and at least partially doped (139) by means of ion implantation from an upper silicon surface comprised in a semiconductor structure (144) down to a depth lower than the depth of the surrounding field oxide (120), and that the semiconductor structure (144) is then heat treated. The trench (126) is achieved by uncovering a predetermined area of the upper silicon surface (109a), etching the semiconductor structure (144) within the predetermined area to a predetermined depth, uniformly depositing a first oxide layer (129), preferably of the type LPCVD-TEOS over the semiconductor structure, especially in the trench, uniformly depositing a barrier layer (130), preferably of silicon nitride, over the first oxide layer (129), filling the trench (126) by depositing a silicon layer (134, 135), which is subsequently etched back, over the nitride layer (130), especially in the trench (126), and thermally growing a cap oxide (136) over the trench filling (134).
(FR) L'invention concerne une broche collectrice et une tranchée d'un circuit intégré destiné à une communication ultrarapide, et un procédé de production de ces éléments. La broche collectrice est réalisée par création d'une zone d'implantation endommagée ou rendue amorphe et dopée (139) au moins partiellement par implantation d'ions depuis une surface de silicium supérieure comprise dans la structure semi-conductrice (144) jusqu'à une profondeur inférieure à la profondeur d'oxyde de champ (120) environnant. La structure semi-conductrice (144) est ensuite soumise à un traitement thermique. La réalisation de la tranchée (126) consiste à laisser à découvert une zone déterminée de la surface de silicium supérieure (109a); à graver la structure semi-conductrice (144) dans cette zone déterminée jusqu'à une profondeur donnée; à déposer de façon uniforme une première couche d'oxyde (129), de préférence de type LPCVD-TEOS sur la structure semiconductrice et notamment dans la tranchée; à déposer uniformement une couche barrière (130), de préférence, de nitrure de silicium, sur la première couche d'oxyde (129); à remplir la tranchée (126) par dépôt sur la couche de nitrure (130) d'une couche de silicium (134, 135) qui est ensuite éliminée par attaque chimique et notamment dans la tranchée (126), et enfin à réaliser la croissance thermique d'une chape d'oxyde (136) sur le remplissage (134) de la tranchée.
Designated States: AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GE, GH, GM, GW, HU, ID, IL, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, UA, UG, UZ, VN, YU, ZW
African Regional Intellectual Property Organization (ARIPO) (GH, GM, KE, LS, MW, SD, SZ, UG, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020010012906EP0985225US20010021559US6251739US20020132439JP2001525998
CN1265225CA2291114AU1998076804