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1. (WO1998053487) PLANARIZATION PROCESS FOR SEMICONDUCTOR SUBSTRATES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1998/053487 International Application No.: PCT/US1998/010479
Publication Date: 26.11.1998 International Filing Date: 21.05.1998
Chapter 2 Demand Filed: 23.10.1998
IPC:
H01L 21/3105 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105
After-treatment
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; 8000 South Federal Way Boise, ID 83706-9632, US
Inventors:
DOAN, Trung, T.; US
BLALOCK, Guy, T.; US
DURCAN, Mark; US
MEIKLE, Scott, G.; US
Agent:
BOND, Laurence, B. ; Trask, Britt & Rossa P.O. Box 2550 Salt Lake City, UT 84110, US
Priority Data:
08/862,75223.05.1997US
Title (EN) PLANARIZATION PROCESS FOR SEMICONDUCTOR SUBSTRATES
(FR) PROCEDE DE PLANARISATION POUR SUBSTRATS SEMI-CONDUCTEURS
Abstract:
(EN) A method of manufacturing semiconductor devices using an improved chemical mechanical planarization processes for the planarization of the surfaces (24) of the wafer (60) on which the semiconductor devices (22) are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating (30) on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through chemical mechanical planarization process.
(FR) L'invention concerne un procédé de fabrication de dispositifs semi-conducteurs employant un procédé amélioré de planarisation chimiques mécaniques en vue de la planarisation des surfaces (24) de la tranche (60) sur laquelle les dispositifs semi-conducteurs (22) sont formés. Le procédé amélioré de planarisation chimique mécanique comporte l'étape consistant à former une surface planaire plate à partir d'un revêtement (30) déformable sur la surface de la tranche, ce revêtement remplissant les irrégularités de surface, avant d'effectuer la planarisation de la surface au moyen d'un procédé de planarisation chimique mécanique.
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Designated States: JP, KR
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020010012837EP1021824JP2001527699