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1. (WO1998053459) SEMICONDUCTOR MEMORY FOR SECURE DATA STORAGE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1998/053459 International Application No.: PCT/US1998/008229
Publication Date: 26.11.1998 International Filing Date: 24.04.1998
IPC:
G11C 16/22 (2006.01) ,G11C 16/28 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
22
Safety or protection circuits preventing unauthorised or accidental access to memory cells
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
26
Sensing or reading circuits; Data output circuits
28
using differential sensing or reference cells, e.g. dummy cells
Applicants:
ATMEL CORPORATION [US/US]; 2325 Orchard Parkway San Jose, CA 95131, US
Inventors:
PATHAK, Saroj; US
PATHAK, Jagdish; US
Agent:
SCHNECK, Thomas; Law Offices of Thomas Schneck P.O. Box 2-E San Jose, CA 95109-0005, US
Priority Data:
08/859,88521.05.1997US
Title (EN) SEMICONDUCTOR MEMORY FOR SECURE DATA STORAGE
(FR) MEMOIRE A SEMI-CONDUCTEURS PERMETTANT UN STOCKAGE SECURISE DES DONNEES
Abstract:
(EN) A memory device includes a memory cell (102) whose data state is sensed by a sense amplifier (100). A balance amplifier (200) having the same construction as the sense amplifier is utilized to sense a balance cell (202) having the same construction as the memory cell. The balance cell is maintained in a erased (conductive) state. The balance cell is gated by the output of the sense amplifier. Such a device operates in a way to consume the same amount of power regardless of the data state of the memory cell. In one embodiment of the invention, a memory device consisting of a memory array includes a balance circuit associated with each of the sense amplifiers in the memory device. In another embodiment of the invention, a trim circuit (208) is used to adjust the conductivity of the balance circuit. This allows the balance circuit to be fine tuned during manufacture to compensate for process variations, thus allowing the balance circuit to be matched to the memory cells.
(FR) La présente invention concerne un dispositif de mémoire comprenant une cellule mémoire (102) dont l'état des données est lu par un amplificateur de lecture (100). Un amplificateur de compensation (200) de même construction que l'amplificateur de lecture assure la lecture d'une cellule de compensation (202) de même construction que la cellule de mémoire. Cette cellule de compensation, qui est maintenue à l'état effacé (conducteur), est commandée par la sortie de l'amplificateur de lecture. Un tel dispositif est capable de fonctionner de façon à toujours consommer la même quantité d'énergie, quel que soit l'état de la cellule de mémoire. Selon une réalisation de l'invention, le dispositif de mémoire est constitué d'une matrice mémoire comportant un circuit de compensation pour chacun de ses amplificateurs de lecture. Selon une autre réalisation de l'invention, on utilise un circuit d'ajustage (208) pour corriger la conductivité du circuit de compensation. Cela permet d'obtenir un accord fin du circuit de compensation pendant la fabrication, de façon à corriger les écarts imputables au traitement, ce qui permet d'adapter parfaitement le circuit de compensation aux cellules mémoire.
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Designated States: CA, CN, JP, KR, NO, SG
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
NO19990229KR1020000029439SG61164EP0914660JP2000515669 CN1226991
CA2261785