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1. (WO1998052278) AN AMPLIFIED MOS BIASING CIRCUIT FOR AVOIDING LATCH-UP

Pub. No.:    WO/1998/052278    International Application No.:    PCT/IB1998/000405
Publication Date: Fri Nov 20 00:59:59 CET 1998 International Filing Date: Fri Mar 20 00:59:59 CET 1998
IPC: G05F 3/24
H03F 1/32
H03F 3/45
Applicants: KONINKLIJKE PHILIPS ELECTRONICS N.V.
PHILIPS NORDEN AB
Inventors: WOMACK, Richard
Title: AN AMPLIFIED MOS BIASING CIRCUIT FOR AVOIDING LATCH-UP
Abstract:
An amplified MOS biasing apparatus and method for avoiding latch-up within an integrated circuit. An amplifier (302) receives a plurality of voltages and multiplies the voltages by a gain so as to generate a plurality of amplified voltages. A comparator (304) compares the plurality of voltages and generates signals indicating which is greatest and which is smallest. A switch (306) connects the greatest of the voltages to N-wells in PMOS transistors and connects the smallest of the voltages to P-wells in NMOS transistors to discourage parasitic diodes, within the PMOS and NMOS transistors, from conducting excessive amounts of current.