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1. (WO1998052278) AN AMPLIFIED MOS BIASING CIRCUIT FOR AVOIDING LATCH-UP
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1998/052278 International Application No.: PCT/IB1998/000405
Publication Date: 19.11.1998 International Filing Date: 19.03.1998
IPC:
G05F 3/24 (2006.01) ,H03F 1/32 (2006.01) ,H03F 3/45 (2006.01)
G PHYSICS
05
CONTROLLING; REGULATING
F
SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
3
Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
02
Regulating voltage or current
08
wherein the variable is dc
10
using uncontrolled devices with non-linear characteristics
16
being semiconductor devices
20
using diode-transistor combinations
24
wherein the transistors are of the field-effect type only
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
1
Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
32
Modifications of amplifiers to reduce non-linear distortion
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
45
Differential amplifiers
Applicants:
KONINKLIJKE PHILIPS ELECTRONICS N.V. [NL/NL]; Groenewoudseweg 1 NL-5621 BA Eindhoven, NL
PHILIPS NORDEN AB [SE/SE]; Kottbygatan 7 Kista S-164 85 Stockholm, SE (SE)
Inventors:
WOMACK, Richard; NL
Agent:
KOPPEN, Jan; Internationaal Octrooibureau B.V. P.O. Box 220 NL-5600 AE Eindhoven, NL
Priority Data:
08/854,71112.05.1997US
Title (EN) AN AMPLIFIED MOS BIASING CIRCUIT FOR AVOIDING LATCH-UP
(FR) CIRCUIT DE POLARISATION MOS AMPLIFIE, CONÇU POUR EMPECHER LE VERROUILLAGE A L'ETAT PASSANT
Abstract:
(EN) An amplified MOS biasing apparatus and method for avoiding latch-up within an integrated circuit. An amplifier (302) receives a plurality of voltages and multiplies the voltages by a gain so as to generate a plurality of amplified voltages. A comparator (304) compares the plurality of voltages and generates signals indicating which is greatest and which is smallest. A switch (306) connects the greatest of the voltages to N-wells in PMOS transistors and connects the smallest of the voltages to P-wells in NMOS transistors to discourage parasitic diodes, within the PMOS and NMOS transistors, from conducting excessive amounts of current.
(FR) L'invention concerne un appareil de polarisation MOS amplifié et un procédé pour empêcher le verrouillage à l'état passant dans un circuit intégré. Un amplificateur (302) reçoit plusieurs tensions et les multiplie par un gain de sorte que plusieurs tensions amplifiées soient générées. Un comparateur (304) compare les tensions et génère des signaux indiquant la tension la plus haute et la plus faible. Un commutateur (306) connecte les tensions les plus hautes à des puits de type N dans les transistors PMOS et connecte les tensions les plus basses à des puits de type P dans des transistors NMOS pour empêcher les diodes parasites, au sein des transistors PMOS et NMOS, de conduire des quantités excessives de courant.
Designated States: JP, KR
European Patent Office (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020000023610EP0923806JP2000514982