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1. (WO1998052231) REDUCE WIDTH, DIFFERENTIALLY DOPED VERTICAL JFET DEVICE
Latest bibliographic data on file with the International Bureau

Considered void 05.11.1998


Pub. No.: WO/1998/052231 International Application No.: PCT/US1998/009227
Publication Date: 19.11.1998 International Filing Date: 06.05.1998
IPC:
H01L 27/07 (2006.01) ,H01L 27/085 (2006.01) ,H01L 29/10 (2006.01) ,H01L 29/808 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
06
including a plurality of individual components in a non-repetitive configuration
07
the components having an active region in common
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
10
with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
80
with field effect produced by a PN or other rectifying junction gate
808
with a PN junction gate
Applicants:
HARRIS CORPORATION [US/US]; 1025 West Nasa Boulevard Melbourne, FL 32919, US
Inventors:
YOUNG, William, R.; US
Agent:
NIYOGI, Bidyut, K.; Harris Corporation International Patent Operations 1025 West Nasa Boulevard MS80 Melbourne, FL 32919, US
Priority Data:
08/855,38513.05.1997US
Title (EN) REDUCE WIDTH, DIFFERENTIALLY DOPED VERTICAL JFET DEVICE
(FR) COMPOSANT A TRANSISTOR VERTICAL A EFFET DE CHAMP A JONCTION PRESENTANT UNE LARGEUR LIMITEE ET UN DOPAGE DIFFERENTIEL
Abstract:
(EN) A load device for an MOS transistor, such as that of a memory cell, includes a differentially doped vertical JFET structure that contains two separate and distinct opposite conductivity type regions. The interior region has the same conductivity as the well in which the JFET is formed, and is surrounded by the JFET channel region which has an annular shape. The pinch-off voltage of the annular vertical JFET channel is established by its cross-sectional thickness and doping profile. This reduced thickness, annular-shaped, vertical JFET channel provides a limited current flow path that can be precisely tailored to restrict current flow to what is essentially a leakage current path, and provide a high load impedance.
(FR) Composant de charge conçu pour un transistor MOS, tel que celui d'une cellule de mémoire, et comprenant une structure de transistor vertical à effet de champ à jonction (JFET) à dopage différentiel contenant deux zones séparées et distinctes dont les types de conductivité sont contraires. La zone intérieure possède la même conductivité que le puits dans lequel est situé le JFET et est entourée par la zone de canal de JFET présentant une forme annulaire. La tension de pincement du canal annulaire du JFET vertical est établie par l'épaisseur de sa section transversale et par son profil de dopage. Ce canal de JFET vertical, d'épaisseur limitée et de forme annulaire permet d'obtenir un trajet limité d'écoulement de courant pouvant être personnalisé avec précision afin de limiter l'écoulement de courant à ce qui est essentiellement un trajet de courant de fuite et de produire une impédance de charge élevée.
Designated States: AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GE, GH, GM, GW, HU, ID, IL, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, UA, UG, UZ, VN, YU, ZW
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
AU1998073701