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1. (WO1998052215) SPACER STRUCTURE AS TRANSISTOR GATE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1998/052215 International Application No.: PCT/US1998/006889
Publication Date: 19.11.1998 International Filing Date: 07.04.1998
IPC:
H01L 21/28 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
ADVANCED MICRO DEVICES, INC. [US/US]; One AMD Place Mail Stop 68 Sunnyvale, CA 94088-3453, US
Inventors:
GARNDER, Mark, I.; US
SPIKES, Thomas, E.; US
Agent:
DRAKE, Paul, S.; Advanced Micro Devices, Inc. 5204 East Ben White Boulevard Mail Stop 562 Austin, TX 78741, US
Priority Data:
08/857,62816.05.1997US
Title (EN) SPACER STRUCTURE AS TRANSISTOR GATE
(FR) STRUCTURE D'ESPACEMENT SERVANT DE GRILLE DE TRANSISTOR
Abstract:
(EN) A semiconductor process in which a spacer support stucture is then formed on an upper surface of a semiconductor substrate. The semiconductor substrate includes a channel region that is laterally displaced between first and second source/drain regions. The spacer support structure includes a substantially vertical sidewall that is laterally aligned over a boundary between the first source/drain region and the channel region of the semiconductor substrate. A gate dielectric is then grown and a transistor gate fabricated by forming a first spacer structure on the sidewall of the spacer support structure. The first spacer structure includes a substantially vertical first sidewall in contact with the spacer support structure sidewall and further includes a second sidewall that is laterally aligned over a boundary between the channel region and the second source/drain region of the semiconductor substrate. The spacer support structure is then removed and source/drain impurity distributions are introduced into the source/drain regions of the semiconductor substrate.
(FR) L'invention porte sur un procédé de fabrication de semi-conducteurs où une structure porteuse d'espacement est formée sur la surface supérieure d'un substrat semi-conducteur. Ledit substrat comporte une région canal latéralement déplacée entre la première et la deuxième région source/drain. La structure porteuse d'espacement présente une paroi latérale sensiblement verticale alignée latéralement sur la limite séparant la première région source/drain de la région canal du substrat semi-conducteur. On fait ensuite croître un diélectrique de grille, puis on constitue une grille de transistor par formation d'une première structure d'espacement sur la paroi latérale de la structure porteuse d'espacement. La première structure d'espacement comporte une première paroi latérale sensiblement verticale en contact avec la paroi latérale de la structure porteuse d'espacement ainsi qu'une deuxième paroi latérale alignée latéralement sur la limite séparant la deuxième région source/drain de la région canal du substrat semi-conducteur. La structure porteuse d'espacement est ensuite éliminée, et on introduit dans les régions source/drain du substrat semi-conducteur des distributions d'impuretés pour source/drain.
front page image
Designated States: JP, KR
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)