Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO1998052112) BIAS GENERATOR FOR A LOW CURRENT DIVIDER
Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

CLAIMS:

1. A voltage divider circuit comprising:
a first plurality of serially coupled transistors including a first transistor for receiving an input voltage and a second transistor for providing an output voltage; and
a second plurality of serially coupled transistors coupled to receive the input voltage and including predetermined ones having substrate terminals respectively coupled to source terminals of said predetermined ones of said second plurality of transistors and respectively coupled to substrate terminals of predetermined ones of said first plurality of transistors, for providing a substrate bias voltage to each of said predetermined ones of said first plurality of transistors.
2. The voltage divider of claim 1, wherein said first plurality of serially coupled transistors have respective drain terminals, each coupled to a respective gate.
3. The voltage divider of claim 2, wherein said second plurality of serially coupled transistors have respective drain terminals, each coupled to a respective gate.
4. The voltage divider of claim 3, wherein said second plurality of serially coupled transistors includes a first transistor and a second transistor, said first transistor having a source coupled to receive said input voltage and a gate, and said second transistor having a drain coupled to ground and coupled to said gate of said first transistor.
5. The voltage divider of claim 4, further comprising a current source coupled to said gate of said first transistor and said drain of said second transistor.
6. A voltage divider comprising:
divider means for receiving an input voltage and providing as output a predetermined portion of said input voltage;
means for providing a substrate bias voltage to said divider means.
7. The voltage divider of claim 6, wherein said divider means includes a plurality of serially coupled transistors, each having a source terminal, and said voltage divider further comprises means for preventing said source terminals from forward biasing.

8. The voltage divider of claim 6, wherein said divider means includes a plurality of serially coupled transistors, each having a source terminal, and said voltage divider further comprises means for supplying current to said divider means to prevent said source terminals from forward biasing.
9. A voltage divider circuit comprising:
a first transistor having a gate, a source terminal for receiving an input voltage, a drain terminal coupled to said gate, and a substrate terminal coupled to said source terminal;
a second transistor having a gate, a substrate terminal, a source terminal coupled to said drain terminal of said first transistor, and a drain terminal coupled to said gate and for providing an output voltage;
a third transistor having a gate, a substrate terminal, a source terminal coupled to said drain terminal of said second transistor, and a drain terminal coupled to said gate and coupled to ground;
a fourth transistor having a gate, a source terminal for receiving an input voltage, a drain terminal coupled to said gate, and a substrate terminal coupled to said source terminal and coupled to said substrate terminal of said second transistor;
a fifth transistor having a gate, a source terminal coupled to said drain terminal of said fourth transistor, a drain terminal coupled to said gate, and a substrate terminal coupled to said source terminal; and
a sixth transistor having a gate, a source terminal coupled to said drain terminal of said fifth transistor, a drain terminal coupled to said gate, coupled to ground, and coupled to said gate of said fourth transistor, and a substrate terminal coupled to said source terminal and coupled to said substrate terminal of said third transistor;
10. The circuit of claim 9, further comprising a current source coupled to said drain of said sixth transistor and coupled to said gate of said fourth transistor.