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Machine translation
1. (WO1998052111) VOLTAGE REGULATING CIRCUIT FOR ELIMINATING 'LATCH-UP
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1998/052111    International Application No.:    PCT/EP1998/002749
Publication Date: 19.11.1998 International Filing Date: 11.05.1998
Chapter 2 Demand Filed:    03.12.1998    
IPC:
G05F 1/575 (2006.01)
Applicants: EM MICROELECTRONIC-MARIN S.A. [CH/CH]; Rue des Sors 3, CH-2074 Marin (CH) (For All Designated States Except US).
PONZETTA, Antonio, Martino [IT/CH]; (CH) (For US Only)
Inventors: PONZETTA, Antonio, Martino; (CH)
Agent: ICB; Ingénieurs Conseils en Brevets S.A., Rue des Sors 3, CH-2074 Marin (CH)
Priority Data:
97107722.7 12.05.1997 EP
Title (EN) VOLTAGE REGULATING CIRCUIT FOR ELIMINATING 'LATCH-UP
(FR) CIRCUIT DE REGULATION DE TENSION DESTINE A SUPPRIMER UN PHENOMENE DIT 'LATCH-UP'
Abstract: front page image
(EN)The invention concerns a voltage regulating circuit (1) capable of detecting 'latch-up' disturbing the voltage to be regulated, eliminating said phenomenon and restoring the voltage at a predetermined level. Said circuit comprises a bipolar transistor (2), a resistor (5) and means supplying substantially constant voltage (6). Said circuit (1) also comprises voltage detecting means (11) arranged to receive the regulated voltage (Vreg), and supply a control voltage to said transistor (2) capable of controlling its being switched between a conductive state and a locked state, such that the transistor (2) is in locked state when a 'latch-up' occurs causing the regulated voltage to fall below a first voltage level, and such that the transistor (2) is in conductive state, when said regulated voltage is lower than a second voltage level, below which the 'latch-up' phenomenon is eliminated.
(FR)La présente invention concerne un circuit (1) de régulation de tension pouvant détecter un phénomène 'latch-up' perturbant la tension à réguler, supprimer ce phénomène et rétablir la tension à un niveau prédéterminé, ce circuit comprenant un transistor bipolaire (2), une résistance (5) et des moyens de fourniture de tension sensiblement constante (6). Ce circuit (1) comprend également des moyens de détection de tension (11) agencés pour recevoir la tension régulée (Vreg), et fournir une tension de commande audit transistor (2) pouvant commander sa commutation entre un état conducteur et un état bloqué, de sorte que le transistor (2) est dans l'état bloqué quand un phénomène 'latch-up' amène ladite tension régulée à chuter en-dessous d'un premier niveau de tension, et que le transistor (2) est dans l'état conducteur, quand ladite tension régulée est inférieure à un second niveau de tension, niveau en-dessous duquel le phénomène 'latch-up' est supprimé.
Designated States: CA, JP, KR, US.
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE).
Publication Language: French (FR)
Filing Language: French (FR)