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1. (WO1998051012) OUTPUT BUFFER CIRCUIT

Pub. No.:    WO/1998/051012    International Application No.:    PCT/JP1997/001506
Publication Date: Fri Nov 13 00:59:59 CET 1998 International Filing Date: Fri May 02 01:59:59 CEST 1997
IPC: H03K 19/00
Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA

TANIGUCHI, Hideki

Inventors: TANIGUCHI, Hideki

Title: OUTPUT BUFFER CIRCUIT
Abstract:
In order to prevent a through current from flowing to a set of MOS transistors in the final stage constituting a push-pull buffer circuit, a reset circuit which performs delaying operation and logic decision by separately receiving signals from two inverter gate groups of a control system and output system arranged in the preceding stage of the transistors is provided. Therefore, the flowing of the through current to the transistors can be prevented even when an input-output circuit consistinng of two power source systems becomes unstable when the power sources are turned on or off and such logic on which a through current flows to the final stage due to a signal output of a signal level converting circuit is generated because the rest circuit forcibly cancels the logic by applying feedback.