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1. (WO1998050960) FLOATING GATE MEMORY CELL WITH CHARGE LEAKAGE PREVENTION
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1998/050960 International Application No.: PCT/US1998/008709
Publication Date: 12.11.1998 International Filing Date: 30.04.1998
IPC:
H01L 21/8247 (2006.01) ,H01L 29/423 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8246
Read-only memory structures (ROM)
8247
electrically-programmable (EPROM)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
Applicants:
ATMEL CORPORATION [US/US]; 2325 Orchard Parkway San Jose, CA 95131, US
Inventors:
LARSEN, Bradley, J.; US
WU, Tsung-Ching; US
Agent:
SCHNECK, Thomas; Law Offices of Thomas Schneck P.O. Box 2-E San Jose, CA 95109-0005, US
Priority Data:
08/853,69109.05.1997US
Title (EN) FLOATING GATE MEMORY CELL WITH CHARGE LEAKAGE PREVENTION
(FR) CELLULE MEMOIRE A GRILLE FLOTTANTE PREVENANT LES FUITES DE CHARGES
Abstract:
(EN) A process for fabricating a floating gate memory cell (60) with reduced charge leakage. An oxide regrowth (73) is formed over the sides of the floating gate (69) and is then covered with an oxide protective coating (64, 66). The structure is applicable to salicide and non-salicide memory cells and is especially useful in floating gate memory cells with gate stacks having abnormally shaped side walls.
(FR) L'invention porte sur un procédé de fabrication d'une cellule mémoire (60) à grille flottante à fuites de charges réduites. Une surépaisseur (73) d'oxyde est formée sur les côtés de la grille flottante (69) puis recouverte d'un revêtement protecteur de l'oxyde (64, 66). Cette structure peut s'appliquer aux cellules de mémoire à siliciure ou sans siliciure, et en particulier aux cellules mémoires à grille flottante dont les empilements de la grille présentent des parois latérales de forme anormale.
front page image
Designated States: CA, CN, JP, KR, NO, SG
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
NO19990075KR1020000023619SG61121EP0934603JP2000513879 CN1227001
CA2259631MYPI 98002051