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1. (WO1998049723) METHOD OF PLANARIZING THE UPPER SURFACE OF A SEMICONDUCTOR WAFER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1998/049723 International Application No.: PCT/US1998/008693
Publication Date: 05.11.1998 International Filing Date: 30.04.1998
Chapter 2 Demand Filed: 07.10.1998
IPC:
B24B 37/22 (2012.01) ,B24B 37/24 (2012.01) ,B24D 11/00 (2006.01) ,H01L 21/304 (2006.01) ,H01L 21/3105 (2006.01) ,H01L 21/321 (2006.01) ,H01L 21/768 (2006.01)
B PERFORMING OPERATIONS; TRANSPORTING
24
GRINDING; POLISHING
B
MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
37
Lapping machines or devices; Accessories
11
Lapping tools
20
Lapping pads for working plane surfaces
22
characterised by a multi-layered structure
B PERFORMING OPERATIONS; TRANSPORTING
24
GRINDING; POLISHING
B
MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
37
Lapping machines or devices; Accessories
11
Lapping tools
20
Lapping pads for working plane surfaces
24
characterised by the composition or properties of the pad materials
B PERFORMING OPERATIONS; TRANSPORTING
24
GRINDING; POLISHING
D
TOOLS FOR GRINDING, BUFFING OR SHARPENING
11
Constructional features of flexible abrasive materials; Special features in the manufacture of such materials
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
304
Mechanical treatment, e.g. grinding, polishing, cutting
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105
After-treatment
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
321
After-treatment
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
Applicants:
MINNESOTA MINING AND MANUFACTURING COMPANY [US/US]; 3M Center P.O. Box 33427 Saint Paul, MN 55133-3427, US (AL, AM, AT, AU, AZ, BA, BB, BE, BF, BG, BJ, BR, BY, CA, CF, CG, CH, CI, CM, CN, CU, CY, CZ, DE, DK, EE, ES, FI, FR, GA, GB, GE, GH, GM, GN, GR, GW, HU, ID, IE, IL, IS, IT, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MC, MD, MG, MK, ML, MN, MR, MW, MX, NE, NL, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, SN, SZ, TD, TG, TJ, TM, TR, TT, UA, UG, UZ, VN, YU, ZW)
KAISAKI, David, A. [US/US]; US (UsOnly)
KRANZ, Heather, K. [US/US]; US (UsOnly)
WOOD, Thomas, E. [US/US]; US (UsOnly)
HARDY, L., Charles [US/US]; US (UsOnly)
Inventors:
KAISAKI, David, A.; US
KRANZ, Heather, K.; US
WOOD, Thomas, E.; US
HARDY, L., Charles; US
Agent:
FEULNER, Gregory, J. ; Minnesota Mining and Manufacturing Company Office of Intellectual Property Counsel P.O. Box 33427 Saint Paul, MN 55133-3427, US
Priority Data:
08/846,72630.04.1997US
Title (EN) METHOD OF PLANARIZING THE UPPER SURFACE OF A SEMICONDUCTOR WAFER
(FR) PROCEDE DE PLANAGE DE LA SURFACE SUPERIEURE D'UNE PLAQUETTE DE SEMI-CONDUCTEUR
Abstract:
(EN) This invention pertains to a method of modifying or refining the surface of a wafer suited for semiconductor fabrication. This method may be used to modify a wafer having an unmodified, exposed surface comprised of a layer of second material deployed over at least one discrete feature of a first material attached to the wafer. A first step of this method comprises contacting and relatively moving the exposed surface of the wafer with respect to an abrasive article, wherein the abrasive article comprises an exposed surface of a plurality of three-dimensional abrasive composite comprising a plurality of abrasive particles fixed and dispersed in a binder and maintaining contact to effect removal of the second material. In a second step, the contact and relative motion are continued until an exposed surface of the wafer has at least one area of exposed first material and at least one area of exposed second material.
(FR) Cette invention concerne à un procédé de modification ou d'affinage de la surface d'une plaquette adaptée à la fabrication d'un semi-conducteur. Ce procédé peut être utilisé pour la modification d'une plaquette présentant une surface exposée, non modifiée, constituée d'une couche d'un second matériau réparti sur au moins une caractéristique discrète d'un premier matériau attaché à la plaquette. La première étape de ce procédé consiste à mettre la surface exposée de la tranche en contact avec un article abrasif et à la déplacer par rapport à ce dernier. Ledit article abrasif comprend une surface exposée constituée d'une pluralité d'un composite abrasif tridimensionnel constitué d'une pluralité de particules abrasives fixes et dispersées dans un liant et maintenant un contact de façon à effectuer l'enlèvement du second matériau. Dans la seconde étape, on prolonge le contact et le mouvement relatif jusqu'à ce qu'une surface exposée de la plaquette présente au moins une partie du premier matériau exposée et au moins une partie du second matériau exposée.
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Designated States: AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GE, GH, GM, GW, HU, ID, IL, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, UA, UG, US, UZ, VN, YU, ZW
African Regional Intellectual Property Organization (ARIPO) (GH, GM, KE, LS, MW, SD, SZ, UG, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020010020384EP1016133US6194317JP2001523395 CN1254441CA2287404
AU1998071706MYPI 98001946