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1. WO1998047331 - WIRING BOARD, WIRING BOARD FABRICATION METHOD, AND SEMICONDUCTOR PACKAGE

Publication Number WO/1998/047331
Publication Date 22.10.1998
International Application No. PCT/JP1998/001748
International Filing Date 16.04.1998
Chapter 2 Demand Filed 13.11.1998
IPC
H01L 21/56 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56Encapsulations, e.g. encapsulating layers, coatings
H01L 23/367 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation
36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
367Cooling facilitated by shape of device
H01L 23/498 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
498Leads on insulating substrates
H01L 23/538 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
538the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/552 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
552Protection against radiation, e.g. light
H01L 23/66 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
58Structural electrical arrangements for semiconductor devices not otherwise provided for
64Impedance arrangements
66High-frequency adaptations
CPC
H01L 21/563
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
H01L 2223/6627
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2223Details relating to semiconductor or other solid state devices covered by the group H01L23/00
58Structural electrical arrangements for semiconductor devices not otherwise provided for
64Impedance arrangements
66High-frequency adaptations
6605High-frequency electrical connections
6627Waveguides, e.g. microstrip line, strip line, coplanar line
H01L 2224/16225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/16235
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
16235the bump connector connecting to a via metallisation of the item
H01L 2224/32225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
Applicants
  • KABUSHIKI KAISHA TOSHIBA [JP]/[JP] (JP, KR)
  • SHIMADA, Osamu [JP]/[JP] (UsOnly)
  • FUKUOKA, Yoshitaka [JP]/[JP] (UsOnly)
  • TAKAGI, Akihiko [JP]/[JP] (UsOnly)
  • SASAOKA, Kenji [JP]/[JP] (UsOnly)
Inventors
  • SHIMADA, Osamu
  • FUKUOKA, Yoshitaka
  • TAKAGI, Akihiko
  • SASAOKA, Kenji
Agents
  • SUYAMA, Saichi
Priority Data
9/9921616.04.1997JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) WIRING BOARD, WIRING BOARD FABRICATION METHOD, AND SEMICONDUCTOR PACKAGE
(FR) TABLEAU DE CONNEXIONS, SON PROCEDE DE FABRICATION ET BOITIER DE SEMI-CONDUCTEUR
Abstract
(EN)
A wiring board provided with a line (1), a shield pattern (2) formed in parallel with the line (1), a conductor layer (4) formed so as to face the line (1) and the shield pattern (2) through an insulating layer (3), a conductor layer (6) formed so as to face the line (1) and the shield pattern (2) through an insulating layer (5), and conductive pillars (7a, 7b) for connecting the conductor layer (4) to the conductor layer (6). The conductive pillars (7a, 7b) are connected to each other through the shield pattern (2). In the above structure, by supplying the ground potential to the shield pattern (2), conductor layers (4, 6), and conductive pillars (7a, 7b), an electromagnetic field is blocked in the direction where the line (1) extends over 360° about the line (1).
(FR)
L'invention concerne un tableau de connexions ayant une ligne (1), une structure de blindage (2) parallèle à la ligne (1), une couche conductrice (4) faisant face à la ligne (1) et à la structure de blindage (2) à travers une couche isolante (3), une couche conductrice (6) faisant face à la ligne (1) et à la structure de blindage (2) à travers une couche isolante (5), et des colonnes conductrices (7a, 7b) pour l'interconnexion des couches conductrices (4) et (6). Les colonnes conductrices (7a, 7b) sont reliées l'une à l'autre via la structure de blindage (2). Dans cette configuration, la fourniture du potentiel de la masse à la structure de blindage (2), aux couches conductrices (4, 6) et aux colonnes conductrices (7a, 7b) a pour effet de bloquer un champ électromagnétique dans la direction où la ligne (1) s'étend, sur 360° autour de la ligne (1).
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