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1. WO1998034276 - METHOD AND DEVICE FOR SEALING IC CHIP

Publication Number WO/1998/034276
Publication Date 06.08.1998
International Application No. PCT/JP1998/000447
International Filing Date 02.02.1998
IPC
H01L 21/00 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L 21/56 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56Encapsulations, e.g. encapsulating layers, coatings
CPC
H01L 21/56
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
H01L 21/563
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
H01L 21/67126
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; ; Apparatus not specifically provided for elsewhere
67005Apparatus not specifically provided for elsewhere
67011Apparatus for manufacture or treatment
67126Apparatus for sealing, encapsulating, glassing, decapsulating or the like
H01L 2224/73203
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
732Location after the connecting process
73201on the same surface
73203Bump and layer connectors
H01L 2224/83102
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
83using a layer connector
831the layer connector being supplied to the parts to be connected in the bonding apparatus
83102using surface energy, e.g. capillary forces
H01L 2224/92125
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
92Specific sequence of method steps
921Connecting a surface with connectors of different types
9212Sequential connecting processes
92122the first connecting process involving a bump connector
92125the second connecting process involving a layer connector
Applicants
  • MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. [JP]/[JP] (AllExceptUS)
  • NISHINO, Kenichi [JP]/[JP] (UsOnly)
  • KANAYAMA, Shinji [JP]/[JP] (UsOnly)
  • OTANI, Hiroyuki [JP]/[JP] (UsOnly)
  • ENCHI, Kohei [JP]/[JP] (UsOnly)
  • YOSHIDA, Hiroyuki [JP]/[JP] (UsOnly)
Inventors
  • NISHINO, Kenichi
  • KANAYAMA, Shinji
  • OTANI, Hiroyuki
  • ENCHI, Kohei
  • YOSHIDA, Hiroyuki
Agents
  • ISHIHARA, Masaru
Priority Data
9/2112604.02.1997JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) METHOD AND DEVICE FOR SEALING IC CHIP
(FR) PROCEDE ET DISPOSITIF POUR LE SCELLEMENT D'UNE PUCE DE CIRCUIT INTEGRE
Abstract
(EN)
A method and device for sealing IC chip, by which the occurence of imperfect sealing can be eleminated by surely feeding a sealing agent onto the upper surface of a mounting substrate. In the method, prior to feeding the sealing agent (17) a first gap (h1) is provided between a feeding nozzle (15) and the substrate (13) mounted with an IC chip (12), and the IC chip (12) is sealed while the sealing agent (17) is fed by providing a second gap (h2) larger than the first gap (h1) between the nozzle (15) and the substrate (13). After the sealing agent (17) is surely brought into contact with the upper surface of the substrate (13), the IC chip (12) is sealed.
(FR)
L'invention concerne un procédé et un dispositif pour sceller une puce de circuit intégré, qui permettent d'éliminer les risques de scellement imparfait en assurant de manière fiable le dépôt d'un agent de scellement à la surface supérieure d'un substrat de fixation. Selon le procédé, avant d'introduire l'agent de scellement (17), on ménage un premier espace (h1) entre une buse d'injection (15) et le substrat (13) où vient se fixer la puce de circuit intégré (12), laquelle sera scellée par l'agent de scellement (17) introduit au moment où un second espace (h2) plus important que le premier espace (h1) est ménagé entre la buse (15) et le substrat (13). Lorsque l'agent de scellement (17) est mis en contact de manière fiable avec la surface supérieure du substrat (13), la puce de circuit intégré (12) est scellée.
Also published as
Latest bibliographic data on file with the International Bureau