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1. (WO1998027583) ELECTRONIC DEVICES AND THEIR MANUFACTURE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1998/027583 International Application No.: PCT/IB1997/001529
Publication Date: 25.06.1998 International Filing Date: 04.12.1997
IPC:
G02F 1/1368 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/45 (2006.01) ,H01L 29/49 (2006.01)
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
45
Ohmic electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
49
Metal-insulator semiconductor electrodes
Applicants:
KONINKLIJKE PHILIPS ELECTRONICS N.V. [NL/NL]; Groenewoudseweg 1 NL - 5621 BA Eindhoven, NL
PHILIPS NORDEN AB [SE/SE]; Kottbygatan 7 Kista S-164 85 Stockholm, SE (SE)
Inventors:
FRENCH, Ian, Douglas; NL
POWELL, Martin, John; NL
Agent:
STEVENS, Brian, T.; Internationaal Octrooibureau B.V. P.O. Box 220 NL-5600 AE Eindhoven, NL
Priority Data:
9626344.719.12.1996GB
Title (EN) ELECTRONIC DEVICES AND THEIR MANUFACTURE
(FR) DISPOSITIFS ELECTRONIQUES ET LEUR FABRICATION
Abstract:
(EN) In the manufacture of a flat panel display or other large-area electronics device, a self-aligned thin-film transistor (TFT) is formed with source and drain silicide parts (31, 32) adjacent an insulated gate structure (25, 21, 22) on a silicon film (20) which provides a transistor body (20a) comprising a channel area (20b) of the transistor. The transistor has its source and drain electrode pattern (11, 12) extending under the silicon film (20). The insulated gate structure (25, 21, 22) is formed as a conductive gate (25) on an insulating film (21, 22) which is patterned together with the conductive gate (25). A silicide-forming metal (30) is deposited over the insulated gate structure (25, 21, 22) and over exposed, adjacent areas (20c and 20d) of the silicon film, and the metal is reacted to form the silicide (31, 32) with these adjacent areas of the silicon film. The unreacted metal is removed from the insulated gate structure (25, 21, 22) by means of a selective etchant to leave the source and drain silicide parts (31 and 32) self-aligned with the conductive gate (25). An electrical connection (n+; 31, 32) is formed across the thickness of the silicon film (20) between the source and drain electrode pattern (11, 12) and the respective source and drain silicide parts (31 and 32).
(FR) La présente invention concerne la fabrication d'un écran plat ou d'autres dispositif électroniques de grande surface, permettant de réaliser un transistor à couche mince (TFT) auto-aligné dont les éléments siliciure source et drain (31, 32) sont adjacents d'une structure de grille (21, 22, 25) sur une couche de silicium (20) venant constituer le corps d'un transistor (20a) dans laquelle se trouve une zone canal (20b) du transistor. Les motifs d'électrodes source et drain (11, 12) du transistor passent sous la couche de silicium (20). La structure de grille isolée (21, 22, 25) vient constituer une grille conductrice (25) sur une couche isolante (21, 22) dont la forme est réalisée en même temps que la grille conductrice (25). Le procédé consiste à déposer, sur la structure de grille isolée (21, 22, 25) ainsi que sur les zones adjacentes découvertes (20c, 20d) de la couche de silicium, un métal de formation de siliciure (30) mis à réagir de façon à former le siliciure (31, 32) avec les zones adjacentes considérées de la couche de silicium. Le procédé consiste ensuite à enlever de la structure de grille isolée (21, 22, 25) le métal n'ayant pas réagi, en utilisant pour cet enlèvement un agent de gravure sélective permettant de conserver les éléments siliciure source et drain (31, 32) en auto-alignement avec la grille conductrice (25). Une connexion électrique (n+; 31, 32) vient se former dans l'épaisseur de la couche de silicium (20) entre le motif d'électrode source et drain (11, 12) et les éléments siliciure source et drain correspondants (31, 32).
Designated States: JP, KR
European Patent Office (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0904601JP2000507050KR1019990087078