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1. WO1998018165 - MEMORY STORAGE CELL AND METHOD OF MANUFACTURING A NON-VOLATILE STORAGE CELL

Publication Number WO/1998/018165
Publication Date 30.04.1998
International Application No. PCT/DE1997/002127
International Filing Date 19.09.1997
Chapter 2 Demand Filed 15.05.1998
IPC
H01L 21/8247 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
8246Read-only memory structures (ROM)
8247electrically-programmable (EPROM)
H01L 27/115 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
H01L 29/423 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40Electrodes
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
CPC
H01L 27/115
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
H01L 27/11517
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
H01L 29/42316
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
42312Gate electrodes for field effect devices
42316for field-effect transistors
Applicants
  • SIEMENS AKTIENGESELLSCHAFT [DE]/[DE] (AllExceptUS)
  • KERBER, Martin [AT]/[DE] (UsOnly)
Inventors
  • KERBER, Martin
Priority Data
196 43 185.918.10.1996DE
Publication Language German (DE)
Filing Language German (DE)
Designated States
Title
(DE) SPEICHERZELLE UND VERFAHREN ZUR HERSTELLUNG EINER NICHTFLÜCHTIGEN SPEICHERZELLE
(EN) MEMORY STORAGE CELL AND METHOD OF MANUFACTURING A NON-VOLATILE STORAGE CELL
(FR) CELLULE DE MEMOIRE ET PROCEDE DE FABRICATION D'UNE CELLULE DE MEMOIRE REMANENTE
Abstract
(DE)
Zur wahlweisen Herstellung einer Dual-Gate-Zelle, einer Split-Gate-Zelle oder einer Stacked-Gate-Zelle wird ein einziges Verfahren angegeben, bei dem in einer ersten Polysiliziumschicht (4) ein Mikrograben (8) erzeugt wird. Der Mikrograben (8) und ein Interpolydieletrikum (10) gewährleisten eine elektrische Isolation von Bereichen der ersten Polysiliziumschicht (4) gegenüber einer zweiten Polysiliziumschicht (11). Durch die Justierung einer Maske (12) kann wahlweise eine der drei Speicherzellen hergestellt werden. Dabei wird außerdem eine Dual-Gate-Zelle mit besonders geringem Platzbedarf geschaffen.
(EN)
A single method is specified for the optional manufacture of a dual-gate cell, a split gate-cell, or a stacked-gate cell, in which a microtrench (8) is created in a first polysilicon layer (4). The microtrench (8) and an interpolydielectric (10) ensure electrical insulation of areas of the first polysilicon layer (4) from a second polysilicon layer (11). By adjusting a mask (12), any one of the three storage cells can be selected for manufacture. In addition, a dual-gate cell requiring exceptionally little space is created.
(FR)
L'invention concerne un procédé permettant de fabriquer, au choix, une cellule à double grille, une cellule à grille en deux parties ou une cellule à grille sous forme de pile. Selon ledit procédé, on crée une microtranchée (8) dans une première couche de silicium polycristallin (4). La microtranchée (8) et un interpolydiélectrique (10) garantissent une isolation électrique de zones de la première couche de silicium polycristallin (4) par rapport à une deuxième couche de silicium polycristallin (11). Grâce à l'ajustage d'un masque (12) il est possible de produire, au choix, une des trois cellules de mémoire susmentionnées. En outre, ledit procédé permet d'obtenir une cellule à double grille d'un encombrement particulièrement faible.
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