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1. WO1998006177 - COMBINED LOGIC GATE AND LATCH

Publication Number WO/1998/006177
Publication Date 12.02.1998
International Application No. PCT/US1997/013618
International Filing Date 05.08.1997
Chapter 2 Demand Filed 03.03.1998
IPC
H03K 3/037 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
3Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02Generators characterised by the type of circuit or by the means used for producing pulses
027by the use of logic circuits, with internal or external positive feedback
037Bistable circuits
H03K 3/356 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
3Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02Generators characterised by the type of circuit or by the means used for producing pulses
353by the use, as active elements, of field-effect transistors with internal or external positive feedback
356Bistable circuits
CPC
H03K 3/037
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
3Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02Generators characterised by the type of circuit or by the means used for producing pulses
027by the use of logic circuits, with internal or external positive feedback
037Bistable circuits
H03K 3/356113
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
3Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02Generators characterised by the type of circuit or by the means used for producing pulses
353by the use, as active elements, of field-effect transistors with internal or external positive feedback
356Bistable circuits
356104using complementary field-effect transistors
356113using additional transistors in the input circuit
Applicants
  • FUJITSU LIMITED [JP]/[JP]
Inventors
  • ASATO, Creighton
Agents
  • MILLERS, David, M.
Priority Data
692,54105.08.1996US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) COMBINED LOGIC GATE AND LATCH
(FR) COMBINAISON DE PORTE LOGIQUE ET DE VERROU
Abstract
(EN) A circuit (300) combines the functions of a logic gate (310, 320) and a latch (330) to lower steady state power dissipation during gate operation. The circuit operates in two modes, a flow-through mode and a latched node. In the flow-through mode, a gate portion (310) which receives one or more digital input signals (X1-XN) implements the complement of a desired Boolean logic function on the input signals and provides an internal signal. The gate portion may have a steady-state power dissipation while providing the internal signal. An inverter (350) in a latch portion (330) of the circuit inverts the internal signal to generate an output signal (Z) which represents the desired logical combination of the input signals. The inverter provides the output signal with a full-range CMOS voltage. In latched mode, the gate portion is disabled to stop the steady-state power dissipation while the latch portion of the circuit preserves the desired output signal.
(FR) Le circuit (300) de la présente invention combine les fonctions d'une porte logique (310, 320) et d'un verrou (330) de façon à diminuer la puissance dissipée en régime permanent lors du fonctionnement de la porte. Ce circuit fonctionne selon deux modes, un mode de transfert et un mode verrouillé. En mode de transfert, une partie faisant office de porte (310), qui reçoit un ou plusieurs signaux d'entrée numériques (X1-XN), met en oeuvre le complément de la fonction logique booléenne désirée sur les signaux d'entrée et délivre un signal interne. Ladite partie faisant office de porte peut dissiper une certaine puissance en régime permanent alors qu'elle délivre le signal interne. Un inverseur (350) d'une partie dudit circuit faisant office de verrou (330) inverse le signal interne de façon à générer un signal de sortie (Z) qui représente la combinaison logique souhaitée des signaux d'entrée. Ledit inverseur délivre le signal de sortie avec une tension CMOS maximale. En mode verrouillé, la porte est désactivée afin d'arrêter la dissipation de puissance en régime permanent pendant que la partie faisant office de verrou maintient le signal de sortie désiré.
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