CLAIMS 1 . A system for transforming an N-bit input value into a transformed N-bit output value comprising: a plurality of linear feedback shift registers (LFSRs) each cyclically generating at its output a subset of all possible N-bit values which is not generated by any other of said LFSRs, the LFSRs together cyclically generating a set of all possible N-bit values; means for comparing each of said N-bit output values that are cyclically generated by said LFSRs to said N-bit input value to determine which of said N-bit output values matches said N-bit input value; and means for selecting as said transformed N-bit output value the output of one of said LFRSs other than the LFSR whose N-bit output value is determined to match said N-bit input value. 2. The system of claim 1 wherein at least some of said LFSRs are arranged in a circular group such that when the N-bit output value of one of the LFSRs in the group is determined to match said N-bit input value, the output of the next LFSR in said circular group is selected as said transformed N-bit output value. 3. The system of claim 2 wherein the LFSRs in said circular group have equal cycle lengths. 4. The system of claim 2 wherein for at least one of the LFSRs in said circular group, the output of the next LFSR in said circular group is selected as said transformed N-bit output value in a cycle following the cycle in which the N-bit output value of said at least one LFSR was determined to match said N-bit input value. 5. The system of claim 2 wherein said transformed N-bit output value is used in error correction coding or ciphering of said N-bit input value. 6. A system for transforming an N-bit input value into a transformed N-bit output value comprising: means for providing a set of all possible N-bit values as a plurality of mutually exclusive subsets each containing at least one possible N-bit value; means for comparing said N-bit input value with each of said subsets to determine to which one of said subsets said N-bit input value belongs; and means for selecting as said transformed N-bit output value an N-bit value from another one of said subsets. 7. The system of claim 6 wherein each of said subsets is cyclically generated in a linear feedback shift register (LFSR). 8. The system of claim 6 wherein each of said subsets is stored in a memory. 9. The system of claim 6 wherein at least some of said subsets are arranged in a circular group such that when said N-bit input value is determined to belong to one of the subsets in said circular group, an output value from the next subset in said circular group is selected as said transformed N-bit output value. 10. The system of claim 6 wherein said transformed N-bit output value is used in error correction coding or ciphering of said N-bit input value. 1 1. A method for transforming an N-bit input value into a transformed N-bit output value comprising the steps of: providing a set of all possible N-bit values as a plurality of mutually exclusive subsets each containing at least one possible N-bit value; comparing said N-bit input value with each of said subsets to determine to which one of said subsets said N-bit input value belongs; and selecting as said transformed N-bit output value an N-bit value from another one of said subsets. 12. The method of claim 11 wherein each of said subsets is cyclically generated in a linear feedback shift register (LFSR). 13. The method of claim 1 1 wherein each of said subsets is stored in a memory.

14. The method of claim 11 wherein at least some of said subsets are arranged in a circular group such that when said N-bit input value is determined to belong to one of the subsets in said circular group, an output value from the next subset in said circular group is selected as said transformed N-bit output value. 15. The method of claim 11 wherein said transformed N-bit output value is used in error correction coding or ciphering of said N-bit input value. 16. A system for transforming an applied N-bit input value into a transformed N-bit output value comprising: memory means for storing for each possible N-bit input value a corresponding N-bit output value which is predetermined by dividing a set of all possible N-bit input values into a plurality of mutually exclusive subsets each containing at least one possible N-bit input value, and by selecting the corresponding N-bit output value for any one possible N-bit input value from a subset other than the one to which said one possible N-bit input value belongs; addressing means for forming from said applied N-bit input value an address to said memory means, said address being associated with a location in said memory means that stores the N-bit output value corresponding to said applied N-bit input value; and means for retrieving from said location the corresponding N-bit output value for use as the transformed N-bit output value. 17. The system of claim 16 wherein said memory means is a read-only-memory (ROM). 18. The system of claim 16 wherein said transformed N-bit output value is used in error correction coding or ciphering of said applied N-bit input value.