WO1997036327 A SEMICONDUCTOR PROCESSING METHOD FOR FORMING A CONTACT PEDESTAL FOR A STORAGE NODE OF A CAPACITOR IN INTEGRATED CIRCUITRY

Settings

Stemming

Single Family Member

Feedback

Goto Application

Publication Number WO/1997/036327

Publication Date 02.10.1997

International Application No. PCT/US1997/004660

International Filing Date 21.03.1997

Chapter 2 Demand Filed 24.10.1997

IPC

H01L 21/8242 2006.01

CPC

H01L 27/10852

Applicants

MICRON TECHNOLOGY, INC. [US]/[US] (AllExceptUS)
DENNISON, Charles, H. [US]/[US] (UsOnly)

Inventors

DENNISON, Charles, H.

Agents

LATWESEN, David

Priority Data

08/622,591

26.03.1996

Publication Language English (EN)

Filing Language English (EN)

Designated States

View all

Title

(EN) A SEMICONDUCTOR PROCESSING METHOD FOR FORMING A CONTACT PEDESTAL FOR A STORAGE NODE OF A CAPACITOR IN INTEGRATED CIRCUITRY

(FR) PROCEDE DE TRAITEMENT DE SEMI-CONDUCTEURS DESTINE A FORMER UN SOCLE DE CONTACT POUR UN POINT NODAL A MEMOIRE D'UN CONDENSATEUR DE CIRCUIT INTEGRE

Abstract

(EN)

A semiconductor processing method of forming a contact pedestal includes: a) providing a node location (28) to which electrical connection is to be made; b) providing insulating dielectric material (30) over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a sufficient degree but not to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer (44) within the opening; f) etching through the contact opening base to outwardly expose the node location; g) filling the contact opening with an electrically conductive material (56); h) rendering the sidewall spacer electrically conductive.

(FR)

L'invention concerne un procédé de traitement de semi-conducteur destiné à former un socle de contact et qui consiste à: a) créer un point nodal (28) sur lequel doit être effectuée une connexion électrique; b) appliquer un matériau diélectrique isolant (30) au-dessus du point nodal; c) créer une ouverture de contact par attaque chimique dans le matériau diélectrique isolant au-dessus du point nodal à un niveau suffisant, mais de façon à ne pas exposer en direction de l'extérieur le point nodal, l'ouverture du contact étant pourvue d'une base; d) créer une couche intercalaire sur le matériau diélectrique isolant à l'intérieur de l'ouverture du contact qui, de par son épaisseur, ne remplit pas complètement l'ouverture du contact; e) effectuer une attaque chimique anisotropique de la couche intercalaire de façon à former un intercalaire en paroi (44) dans l'ouverture; g) remplir l'ouverture du contact avec un matériau électroconducteur (56); h) conférer à la paroi intercalaire des propriétés électro-isolantes.

Also published as

AU1997023422

DE000069731945

EP0891634

JP2000507741

JP2005101666

KR1019990082204

SG54885

US20020020883

US6083831

US6300213

US6312984

US6331725

Latest bibliographic data on file with the International Bureau

H	ELECTRICITY
01	BASIC ELECTRIC ELEMENTS
L	SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21	Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70	Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77	Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78	with subsequent division of the substrate into plural individual devices
82	to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822	the substrate being a semiconductor, using silicon technology
8232	Field-effect technology
8234	MIS technology
8239	Memory structures
8242	Dynamic random access memory structures (DRAM)

H	ELECTRICITY
01	BASIC ELECTRIC ELEMENTS
L	SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21	Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70	Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77	Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78	with subsequent division of the substrate into plural individual devices
82	to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822	the substrate being a semiconductor, using silicon technology
8232	Field-effect technology
8234	MIS technology
8239	Memory structures
8242	Dynamic random access memory structures (DRAM)

H	ELECTRICITY
01	BASIC ELECTRIC ELEMENTS
L	SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27	Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02	including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04	the substrate being a semiconductor body
10	including a plurality of individual components in a repetitive configuration
105	including field-effect components
108	Dynamic random access memory structures
10844	Multistep manufacturing methods
10847	for structures comprising one transistor one-capacitor memory cells
1085	with at least one step of making the capacitor or connections thereto
10852	the capacitor extending over the access transistor

H	ELECTRICITY
01	BASIC ELECTRIC ELEMENTS
L	SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27	Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02	including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04	the substrate being a semiconductor body
10	including a plurality of individual components in a repetitive configuration
105	including field-effect components
108	Dynamic random access memory structures
10844	Multistep manufacturing methods
10847	for structures comprising one transistor one-capacitor memory cells
1085	with at least one step of making the capacitor or connections thereto
10852	the capacitor extending over the access transistor

Processing

National Phase Entries

Authority File

Settings

Feedback

Goto Application

1. WO1997036327 - A SEMICONDUCTOR PROCESSING METHOD FOR FORMING A CONTACT PEDESTAL FOR A STORAGE NODE OF A CAPACITOR IN INTEGRATED CIRCUITRY

WIPO Translate