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1. WO1997034223 - LOGIC ELEMENTS FOR INTERLACED CARRY/BORROW SYSTEMS HAVING A UNIFORM LAYOUT

Publication Number WO/1997/034223
Publication Date 18.09.1997
International Application No. PCT/US1996/003220
International Filing Date 11.03.1996
Chapter 2 Demand Filed 09.10.1997
IPC
G06F 7/50 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
50Adding; Subtracting
CPC
G06F 2207/3876
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2207Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
38Indexing scheme relating to groups G06F7/38 - G06F7/575
3804Details
386Special constructional features
3876Alternation of true and inverted stages
G06F 2207/5063
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2207Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
506Indexing scheme relating to groups G06F7/506 - G06F7/508
50632-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder
G06F 7/508
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
50Adding; Subtracting
505in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
506with simultaneous carry generation for, or propagation over, two or more stages
508using carry look-ahead circuits
Applicants
  • PERKEL, Manley [US]/[US]
  • GRUNDLAND, Nathan [IL]/[IL]
Inventors
  • GRUNDLAND, Nathan
Agents
  • LANGSAM, Andrew, S.
Priority Data
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) LOGIC ELEMENTS FOR INTERLACED CARRY/BORROW SYSTEMS HAVING A UNIFORM LAYOUT
(FR) ELEMENTS LOGIQUES POUR SYSTEMES ENTRELACES DE REPORT DE RETENUE/RETENUE NEGATIVE POSSEDANT UN AGENCEMENT UNIFORME
Abstract
(EN) Logic elements (20) for use in carry/borrow and comparator systems, which operate in accordance with the IMPLY logical relationship. Utilization of the IMPLY logical relationship overcomes the inherent complication of inversion so that it becomes an effective benefit, making possible uniform carry system layouts with uniform logic elements using a newly defined gate pair combination in general. The gate pair logic elements (20) provide a novel carry-propagate signal P which includes a redundant carry-generate signal G, thereby defining a novel carry-integrate signal I (Ao). The novel carry-integrate signal I (Ao) together with the carry-generate signal G (Bo) define a signal pair utilized in succeeding carry levels which are organized in a simplified fashion.
(FR) Cette invention concerne des éléments logiques (20) destinés à des systèmes de comparaison et de report de retenue/retenue négative, lesquels éléments fonctionnent selon la relation logique de type IMPLY. Le recours à cette relation logique permet de surmonter le problème inhérent d'inversion de manière à ce qu'elle devienne un atout efficace. Ce procédé permet ainsi d'obtenir des agencements uniformes de systèmes de report de retenue, dont les éléments logiques uniformes utilisent, en général, une combinaison de paire de grilles récemment définie. Les éléments logiques (20) de paire de grilles permettent d'obtenir un nouveau signal P de propagation de report qui comprend un signal G redondant de génération de report, permettant ainsi de définir un nouveau signal I d'intégration de report (Ao). Le nouveau signal I d'intégration de report (Ao) et le signal G de génération de report (Bo) définissent une paire de signaux utilisés dans des niveaux de report successifs qui sont organisés de manière simplifiée.
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