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1. WO1997032249 - SYSTEM FOR PERFORMING ARITHMETIC OPERATIONS WITH SINGLE OR DOUBLE PRECISION

Publication Number WO/1997/032249
Publication Date 04.09.1997
International Application No. PCT/US1997/003764
International Filing Date 27.02.1997
IPC
G06F 7/48 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
CPC
G06F 2207/3816
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2207Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
38Indexing scheme relating to groups G06F7/38 - G06F7/575
3804Details
3808concerning the type of numbers or the way they are handled
3812Devices capable of handling different types of numbers
3816Accepting numbers of variable word length
G06F 2207/3892
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2207Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
38Indexing scheme relating to groups G06F7/38 - G06F7/575
3804Details
386Special constructional features
3884Pipelining
3892Systolic array
G06F 7/00
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
G06F 7/48
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
Applicants
  • ATMEL CORPORATION [US]/[US]
Inventors
  • MUWAFI, Jumana, A.
  • TOURIGUIAN, Mihran
Agents
  • SCHNECK, Thomas
Priority Data
08/607,93728.02.1996US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) SYSTEM FOR PERFORMING ARITHMETIC OPERATIONS WITH SINGLE OR DOUBLE PRECISION
(FR) SYSTEME POUR EFFECTUER DES OPERATIONS ARITHMETIQUES EN MODE PRECISION SIMPLE OU DOUBLE
Abstract
(EN) An arithmetic manipulation unit (AMU) (Fig. 6) performs arithmetic operations on N-bit words in a single precision mode and on 2N-bit words in a double precision mode. Preferably, the AMU performs a double precision operation in only two pipelined cycles: a first cycle generating a first 2N-bit operand by concatenating two N-bit parts by means of a sign extension unit (42) and multiplexer (MY) (Fig. 7) and loading the operand to an output register (46); and a second cycle in which a second 2N-bit operand is generated (from a second pair of N-bit parts), the first operand is fed back from the output register, and an arithmetic operation is performed on the two operands by an arithmetic logic unit (ALU 44). A system (Fig. 1) including such an AMU circuit preferably also includes a multi-port memory (6) and a memory management unit (MMU 3; Fig. 8) using address pointers (r0-r7) to fetch two N-bit words from the memory in a single cycle.
(FR) Une unité de manipulation arithmétique (AMU) (Fig. 6) effectue des opérations arithmétiques sur des mots à N-bits en mode précision simple et sur des mots à 2N bits en mode de précision double. De préférence, l'AMU effectue une opération en mode de précision double uniquement dans deux cycles pipeline : un premier cycle générant un premier opérande à 2N bits en enchaînant deux parties à N bits au moyen d'une unité d'extension de signe (42) et d'un multiplexeur (MY) et en chargeant l'opérande sur un registre externe (46); et un second cycle dans lequel un second opérande à N bits est généré à partir d'une seconde paire de parties à N bits, le premier opérande est retourné depuis le registre de sortie et une opération arithmétique est faite sur les deux opérandes par une unité logique arighmétique (ALU 44). Un système comprenant un circuit AMU comprend également, de préférence, un mémoire multi-port (6) et une unité de gestion (MMU;3) de la mémoire utilisant des pointeurs d'adresses (r0-r7) pour aller chercher deux mots à N bits de la mémoire en un seul cycle.
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