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1. WO1997031311 - A MICROPROCESSOR CONFIGURED TO DETECT A GROUP OF INSTRUCTIONS AND TO PERFORM A SPECIFIC FUNCTION UPON DETECTION

Publication Number WO/1997/031311
Publication Date 28.08.1997
International Application No. PCT/US1997/002504
International Filing Date 18.02.1997
Chapter 2 Demand Filed 23.09.1997
IPC
G06F 9/38 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
CPC
G06F 9/30181
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30181Instruction operation extension or modification
G06F 9/3455
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
34Addressing or accessing the instruction operand or the result ; ; Formation of operand address; Addressing modes
345of multiple operands or results
3455using stride
G06F 9/382
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3818Decoding for concurrent execution
382Pipelined decoding, e.g. using predecoding
G06F 9/383
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3824Operand accessing
383Operand prefetching
G06F 9/3853
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
3853of compound instructions
Applicants
  • ADVANCED MICRO DEVICES, INC. [US]/[US]
Inventors
  • LYNCH, Thomas, W.
Agents
  • MILLER, Louise
  • BROOKES & MARTIN
Priority Data
08/605,86923.02.1996US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) A MICROPROCESSOR CONFIGURED TO DETECT A GROUP OF INSTRUCTIONS AND TO PERFORM A SPECIFIC FUNCTION UPON DETECTION
(FR) MICROPROCESSEUR CONFIGURE POUR DETECTER UN GROUPE D'INSTRUCTIONS ET EXECUTER UNE FONCTION SPECIFIQUE APRES DETECTION
Abstract
(EN)
A microprocessor is provided which includes a heuristic processing unit configured to detect a predefined group of instructions and to cause the performance of a specific function associated with the group of instructions. The specific function may correspond to the outcome of executing the group of instructions. Alternatively, the specific function may be a set of operations not directly corresponding to the group of instructions, but designed to improve the performance of the sequence of instructions within which the group of instructions is embedded. The heuristic processing unit asserts control signals to dedicated hardware to cause the specific function to be performed. Instruction sequences need not be modified from the instruction set employed by the microprocessor. The microprocessor detects the previously inefficient instruction sequences and performs the corresponding function efficiently.
(FR)
L'invention a trait à un microprocesseur comportant une unité de traitement heuristique configurée pour détecter un groupe prédéterminé d'instructions et exécuter une fonction spécifique associée au groupe d'instructions. La fonction spécifique, qui peut correspondre au résultat de l'exécution du groupe d'instructions, peut également revêtir la forme d'un jeu d'opérations sans correspondance directe avec le groupe d'instructions mais conçu pour améliorer la performance de la séquence d'instructions dont fait partie ce groupe d'instructions. L'unité de traitement heuristique donne confirmation de signaux de commande à un matériel spécialisé en vue de l'exécution de la fonction spécifique. Il n'est pas nécessaire de modifier les séquences d'instructions par rapport au jeu d'instructions utilisées par le microprocesseur. Ce dernier détecte les précédentes séquences d'instructions inefficaces et exécute la fonction correspondante de manière efficace.
Also published as
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