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1. WO1997025742 - MULTI-CHIP INTEGRATED CIRCUIT PACKAGE

Publication Number WO/1997/025742
Publication Date 17.07.1997
International Application No. PCT/US1996/020865
International Filing Date 30.12.1996
Chapter 2 Demand Filed 31.07.1997
IPC
H01L 23/433 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation
42Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
433Auxiliary members characterised by their shape, e.g. pistons
H01L 23/498 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
498Leads on insulating substrates
H01L 25/18 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
CPC
H01L 2224/05553
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0555Shape
05552in top view
05553being rectangular
H01L 2224/48145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
48145the bodies being stacked
H01L 2224/48247
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48245the item being metallic
48247connecting the wire to a bond pad of the item
H01L 2224/8547
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
85using a wire connector
8538Bonding interfaces outside the semiconductor or solid-state body
85399Material
854with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
85463the principal constituent melting at a temperature of greater than 1550°C
8547Zirconium (Zr) as principal constituent
H01L 23/4334
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation ; ; Temperature sensing arrangements
42Fillings or auxiliary members in containers ; or encapsulations; selected or arranged to facilitate heating or cooling
433Auxiliary members ; in containers; characterised by their shape, e.g. pistons
4334Auxiliary members in encapsulations
H01L 23/49861
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements
488consisting of soldered ; or bonded; constructions
498Leads, ; i.e. metallisations or lead-frames; on insulating substrates, ; e.g. chip carriers
49861Lead-frames fixed on or encapsulated in insulating substrates
Applicants
  • INTEL CORPORATION [US]/[US] (AllExceptUS)
  • LODER, William, G. [US]/[US] (UsOnly)
  • McMAHON, John, Francis [US]/[US] (UsOnly)
Inventors
  • LODER, William, G.
  • McMAHON, John, Francis
Agents
  • TAYLOR, Edwin, H.
Priority Data
08/581,02103.01.1996US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MULTI-CHIP INTEGRATED CIRCUIT PACKAGE
(FR) BOITIER DE CIRCUIT INTEGRE MULTIPUCE
Abstract
(EN)
An electronic package which has a plurality of stacked integrated circuit dies. The package includes a first die (12) that is mounted to a die paddle (16) of a lead frame (18). The first die is also connected to the leads of the lead frame by bond wires (28). A second die (14) is mounted to the top surface of the first die and electrically connected to the first die with bond wires. The first die, second die and die paddle are all enclosed by a package.
(FR)
L'invention se rapporte à un boîtier électronique comportant une pluralité de puces de circuit intégré empilées. Ce boîtier comprend une première puce (12) montée sur une plaquette (16) d'un cadre de montage (18). Cette première puce est également connectée aux conducteurs du cadre de montage par des fils de liaison (28). Une seconde puce (14) est montée sur la surface supérieure de la première à laquelle elle est raccordée par des fils de liaison. La première et la seconde puce, et la plaquette sont toutes renfermées dans un boîtier.
Also published as
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