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1. WO1997024725 - HIGH PERFORMANCE UNIVERSAL MULTI-PORT INTERNALLY CACHED DYNAMIC RANDOM ACCESS MEMORY SYSTEM, ARCHITECTURE AND METHOD

Publication Number WO/1997/024725
Publication Date 10.07.1997
International Application No. PCT/IB1996/000794
International Filing Date 12.08.1996
Chapter 2 Demand Filed 14.07.1997
IPC
G06F 12/08 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
G06F 13/16 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G11C 7/10 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
CPC
G06F 12/0893
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0893Caches characterised by their organisation or structure
G06F 13/16
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G11C 7/1075
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1075for multiport memories each having random access ports and serial ports, e.g. video RAM
Applicants
  • CHATTER, Mukesh [IN]/[US]
Inventors
  • CHATTER, Mukesh
Agents
  • RINES, Robert, Harvey
Priority Data
08/581,46729.12.1995US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) HIGH PERFORMANCE UNIVERSAL MULTI-PORT INTERNALLY CACHED DYNAMIC RANDOM ACCESS MEMORY SYSTEM, ARCHITECTURE AND METHOD
(FR) SYSTEME ET ARCHITECTURE DE MEMOIRE RAM DYNAMIQUE POLYVALENTE A CAPACITE ELEVEE POSSEDANT UNE ANTEMEMOIRE INTERNE ET DES ACCES MULTIPLES ET PROCEDE
Abstract
(EN)
A novel low cost/high performance multi-port internally cached dynamic random access memory architecture called 'AMPIC DRAM', and consequentially a unique system architecture which eliminates current serious system bandwidth limitations. It also provides a means to transfer blocks of data internal to the chip, orders of magnitude faster than the traditional approach. The chip also interconnects significantly higher numbers of resources with substantially enhanced performance and at notably lower cost. A system configuration based on this novel architecte can work equally efficiently for both main memory functions and as graphics memory, thus providing a truly low cost, high performance unified memory architecture.
(FR)
Nouvelle architecture de mémoire RAM dynamique économique à capacité élevée possédant une antémémoire interne et des accès multiples, désignée 'AMPIC DRAM' et, de ce fait, architecture unique de système éliminant les limitations habituelles importantes de la largeur de bande du système. L'invention concerne également un moyen de transfert de blocs de données à l'intérieur de la puce, d'ordres d'intensité plus rapides que ceux du processus classique. La puce effectue également l'interconnexion de nombres considérablement plus élevés de ressources associés à des performances sensiblement améliorées et de façon beaucoup plus économique. Une configuration de système basée sur cette nouvelle architecture peut fonctionner avec une efficacité égale pour les deux fonctions de mémoire principale et en tant que mémoire de graphiques, ce qui permet d'obtenir une architecture de mémoire unifiée présentant une réelle économie et une capacité élevée.
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