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1. WO1997023910 - SILICON BIPOLAR JUNCTION TRANSISTOR HAVING REDUCED EMITTER LINE WIDTH

Publication Number WO/1997/023910
Publication Date 03.07.1997
International Application No. PCT/US1996/019962
International Filing Date 17.12.1996
Chapter 2 Demand Filed 21.07.1997
IPC
H01L 21/331 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
328Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors
33the devices comprising three or more electrodes
331Transistors
H01L 29/08 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
08with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
CPC
H01L 29/0804
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
08with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
0804Emitter regions of bipolar transistors
H01L 29/66272
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66234Bipolar junction transistors [BJT]
66272Silicon vertical transistors
Applicants
  • THE WHITAKER CORPORATION [US]/[US]
Inventors
  • TAJADOD, James
  • BOLES, Timothy, Edward
  • NOONAN, Paulette, Rita
Agents
  • FRANCOS, William, S.
Priority Data
08/741,44431.10.1996US
08/742,22431.10.1996US
60/009,13522.12.1995US
60/009,14122.12.1995US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SILICON BIPOLAR JUNCTION TRANSISTOR HAVING REDUCED EMITTER LINE WIDTH
(FR) TRANSISTOR A JONCTION BIPOLAIRE EN SILICIUM A LARGEUR REDUITE DE LIGNE EMETTEUR
Abstract
(EN)
The present invention is drawn to a silicon bipolar junction transistor having emitter line spacings on the order of approximately 0.25 microns or less. The present invention utilizes a conventional structure for a bipolar junction transistor. A layer of silicon dioxide (201) is grown and selectively etched after photolithography, masking and etching techniques in the desired regions for the emitter, collector and base. A layer of silicon nitride (203) is disposed on the layer of silicon dioxide, having been deposited over the entire surface of the wafer containing the etched 0.5 micron width line features at the emitter base and collector sites. Low pressure chemical vapor deposition (LPCVD) enables uniform silicon nitride growth both vertically from the surface and horizontally from the feature sidewalls. The deposited film of silicon nitride is then etched using standard reactive ion etching (RIE) techniques, removing the silicon nitride from horizontal surfaces without removing the silicon nitride from the side walls of the etched patterns. The resultant spacer (400) of silicon nitride is attached to the side wall of the original feature, thereby reducing the window of the original features by a dimension approximately two times the thickness of the deposited silicon nitride.
(FR)
La présente invention se rapporte à un transistor à jonction bipolaire en silicium dont les écartements de lignes émetteur sont approximativement égaux ou inférieurs à 0,25 microns. Cette invention utilise une structure conventionnelle de transistor à jonction bipolaire. Une couche de dioxyde de silicium (201) est tirée et sélectivement gravée selon des procédés de photolithographie, masquage et gravure dans les régions désirées de l'émetteur, du collecteur et de la base. Une couche de nitrure de silicium (203) est déposée sur la couche de dioxyde de silicium qui a été déposée sur toute la surface de la tranche renfermant les structures de ligne gravées au demi-micron au niveau des sites de l'émetteur, de la base et du collecteur. Le dépôt chimique en phase vapeur permet de tirer uniformément le nitrure de silicium à la fois verticalement à partir de la surface et horizontalement à partir des parois latérales de la structure. Le film de nitrure de silicium déposé est ensuite gravé à l'aide de procédés standards de gravure par réaction ionique, par élimination du nitrure de silicium des surfaces horizontales, sauf celui des parois latérales des motifs gravés. Le séparateur (400) de nitrure de silicium obtenu est fixé à la paroi latérale de la structure d'origine, ce qui réduit la dimension d'ouverture des structures d'origine d'approximativement deux fois l'épaisseur du nitrure de silicium déposé.
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