PATENTSCOPE will be unavailable a few hours for maintenance reason on Tuesday 19.11.2019 at 4:00 PM CET
Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO1997023000) SEMICONDUCTOR FIELD EFFECT DEVICE COMPRISING A SiGe LAYER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1997/023000 International Application No.: PCT/IB1996/001301
Publication Date: 26.06.1997 International Filing Date: 26.11.1996
IPC:
H01L 21/336 (2006.01) ,H01L 21/8238 (2006.01) ,H01L 29/10 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
10
with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Applicants:
PHILIPS ELECTRONICS N.V. [NL/NL]; Groenewoudseweg 1 NL-5621 BA Eindhoven, NL
PHILIPS NORDEN AB [SE/SE]; Kottbygatan 7 Kista S-164 85 Stockholm, SE (SE)
Inventors:
SCHMITZ, Jurriaan; NL
WOERLEE, Pierre, Hermanus; NL
Agent:
HOUBIERS, Ernest, E., M., G.; Internationaal Octrooibureau B.V. P.O. Box 220 NL-5600 AE Eindhoven, NL
Priority Data:
95203512.915.12.1995EP
Title (EN) SEMICONDUCTOR FIELD EFFECT DEVICE COMPRISING A SiGe LAYER
(FR) DISPOSITIF A EFFET DE CHAMP ET A SEMI-CONDUCTEURS COMPORTANT UNE COUCHE DE SiGe
Abstract:
(EN) To obtain a high mobility and a suitable threshold voltage in MOS transistors with channel dimensions in the deep sub-micron range, it is desirable to bury a strongly doped layer (or ground plane) in the channel region below a weakly doped intrinsic surface region, a few tens of nm below the surface. It was found, however, that degradation of the mobility can occur particularly in n-channel transistors owing to diffusion of boron atoms from the strongly doped layer to the surface, for example during the formation of the gate oxide. To prevent this degradation, a thin layer (11) of Si1-xGex inhibiting boron diffusion is provided between the strongly doped layer (10) and the intrinsic surface region (7), for example with x = 0.3. The SiGe layer and the intrinsic surface region may be provided epitaxially, the thickness of the SiGe layer being so small that the lattice constants in the epitaxial layers do not or substantially not differ from those in the substrate 1 in a plane parallel to the surface, while a sufficient diffusion-inhibiting effect is retained. Since SiGe has a diffusion-accelerating rather than decelerating effect on n-type dopants, the ground plane of a p-channel transistor in a CMOS embodiment is doped with As or Sb because of the low diffusion rate of these elements in pure silicon.
(FR) Il est recommandé, pour obtenir une grande mobilité ainsi qu'une tension de seuil convenable dans un transistor MOS à canaux d'une taille comprise dans la gamme submicronique profonde, de noyer une couche fortement dopée (ou un plan de masse) dans la zone du canal se trouvant sous une région superficielle intrinsèque faiblement dopée, à quelques dizaines de nm sous la surface. Il a été, toutefois, établi qu'une perte de mobilité pouvait survenir, notamment, dans des transistors à canal N, du fait de la diffusion d'atomes de bore, de la couche fortement dopée vers la surface, durant la formation de l'oxyde de grille par exemple. Pour empêcher cette perte de mobilité, on place, entre la couche fortement dopée (10) et la région superficielle intrinsèque (7), une fine couche (11) de Si1-xGex inhibant la diffusion de bore, x ayant par exemple une valeur égale à 0,3. La couche de silicium-germanium (SiGe) et la région superficielle intrinsèque peuvent être installées épitaxialement, l'épaisseur de la couche de SiGe étant suffisamment faible pour que les constantes du réseau cristallin dans les couches épitaxiales ne diffèrent pas ou quasiment pas des constantes du substrat (1) dans un plan parallèle à la surface et un effet d'inhibition de diffusion suffisant étant conservé. Dans la mesure où le SiGe est doué d'un effet d'accélération de diffusion plutôt que de ralentissement sur des dopants de type N, on dope, dans un dispositif MOS compatible, le plan de masse d'un transistor à canal P à l'arsenic ou à l'antimoine en raison de la faible vitesse de diffusion des ces éléments dans du silicium pur.
Designated States: JP, KR
European Patent Office (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0809865JPH11500873KR1019980702309