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Machine translation
1. (WO1997021247) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1997/021247    International Application No.:    PCT/JP1996/003469
Publication Date: 12.06.1997 International Filing Date: 27.11.1996
Chapter 2 Demand Filed:    27.11.1996    
IPC:
H01L 27/092 (2006.01), H01L 27/11 (2006.01)
Applicants: HITACHI, LTD. [JP/JP]; 6, Kanda Surugadai 4-chome, Chiyoda-ku, Tokyo 101 (JP) (For All Designated States Except US).
NAKAYAMA, Michiaki [JP/JP]; (JP) (For US Only).
HAMAMOTO, Masato [JP/JP]; (JP) (For US Only).
MORI, Kazutaka [JP/JP]; (JP) (For US Only).
ISOMURA, Satoru [JP/JP]; (JP) (For US Only)
Inventors: NAKAYAMA, Michiaki; (JP).
HAMAMOTO, Masato; (JP).
MORI, Kazutaka; (JP).
ISOMURA, Satoru; (JP)
Agent: TSUTSUI, Yamato; Tsutsui & Associates, N.S. Excel 301, 22-45, Nishishinjuku 7-chome, Shinjuku-ku, Tokyo 160 (JP)
Priority Data:
7/315459 04.12.1995 JP
Title (EN) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME
(FR) CIRCUIT INTEGRE A SEMI-CONDUCTEURS ET SON PROCEDE DE FABRICATION
Abstract: front page image
(EN)A semiconductor integrated circuit device having a CMOS circuit, in which an n-type well (2) where one transistor T¿p? constituting the CMOS circuit is provided is electrically connected to a first power supply voltage line Vdd through a switching transistor Tps and a p-type well (3) where the other transistor Tn constituting the CMOS circuit is provided is electrically connected to a second power supply voltage line Vss through a switching transistor Tns. Thus, thermal runaway of the device due to leak current during the test is prevented by turning off the transistors Tps and Tns and supplying potentials suitable for the tests to the wells (2 and 3) from the outside. While the device is normally operated, latch up and variation of the operating speed of the device is prevented by turning on the transistors Tps and Tns and respectively setting the wells (2 and 3) at power supply voltages Vdd and Vss.
(FR)L'invention porte sur un dispositif à circuit intégré CMOS à semi-conducteurs comportant un puits de type n (2) où l'un T¿p? des transistors constitutifs du circuit est raccordé électriquement à une première source de tension Vdd par l'intermédiaire d'un transistor de commutation Tps, et comportant un puits de type p (3) où l'autre transistor (Tn) constitutif du circuit est raccordé électriquement à une deuxième source de tension Vss par l'intermédiaire d'un transistor de commutation Tns. On peut ainsi empêcher, lors des essais, les pertes thermiques du circuit dues aux courants de fuite en bloquant les transistors Tps et Tsn et en fournissant de l'extérieur aux puits (2) et (3) les tensions d'essai requises. En fonctionnement normal, on peut empêcher le verrouillage et les variations de la vitesse de fonctionnement du dispositif en débloquant les transistors Tps et Tsn et en fournissant respectivement aux puits (2) et (3) les tensions Vdd et Vss.
Designated States: CN, JP, KR, SG, US.
European Patent Office (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)