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Machine translation
1. (WO1997020316) AUTOMATED PROCESS FOR GENERATING BOARDS FROM DEFECTIVE CHIPS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1997/020316    International Application No.:    PCT/IL1996/000171
Publication Date: 05.06.1997 International Filing Date: 28.11.1996
IPC:
G11C 29/00 (2006.01)
Applicants: MEMSYS LTD. [IL/IL]; 21 Havaad Haleumi Street, P.O. Box 16031, 91160 Jerusalem (IL) (For All Designated States Except US).
FRIEDMAN, Yaakov [IL/IL]; (IL) (For US Only).
SCHNEIDER, Mark [IL/IL]; (IL) (For US Only).
SUTZKEVER, Efim [IL/IL]; (IL) (For US Only).
COEL, Craig, M. [US/IL]; (IL) (For US Only)
Inventors: FRIEDMAN, Yaakov; (IL).
SCHNEIDER, Mark; (IL).
SUTZKEVER, Efim; (IL).
COEL, Craig, M.; (IL)
Agent: LEWIN, Aaron; Silber, Schottenfels, Gerber & Lewin, 29B Keren Hayesod Street, 94188 Jerusalem (IL)
Priority Data:
116220 30.11.1995 IL
Title (EN) AUTOMATED PROCESS FOR GENERATING BOARDS FROM DEFECTIVE CHIPS
(FR) PROCEDE AUTOMATISE D'ELABORATION DE CIRCUITS AU MOYEN DE PUCES DEFECTUEUSES
Abstract: front page image
(EN)An automated apparatus for generating a plurality of memory systems from a population of memory elements (90) including non-perfect memory elements each including at least one defective memory cell, the apparatus comprising: a region tester (80) operative to test regions within each non-perfect memory element for defective cells and to generate a regional testing result for each non-perfect memory element; a memory element grouper (100) operative to group the population of memory elements into a plurality of sets based on the regional testing results; and a controlling program generator (140) operative to automatically generate a controlling program for a programmable controller within a memory system, the memory system also including the memory elements in an individual one of the plurality of sets.
(FR)L'invention porte sur un procédé automatisé d'élaboration de systèmes de mémoires à partir de séries d'éléments de mémoire présentant des imperfections. Ledit procédé consiste: à tester les différentes zones des éléments de mémoire imparfaits pour déceler les cellules défectueuses; à élaborer pour chacune des zones des éléments de mémoire imparfaits une topographie des résultats; à regrouper les éléments de mémoire en ensembles en fonction des résultats; puis à programmer automatiquement un contrôleur pour chaque système de mémoire comprenant au moins l'un des susdits ensembles.
Designated States: CN, JP, KR, US.
European Patent Office (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE).
Publication Language: English (EN)
Filing Language: English (EN)