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1. (WO1997019467) SIDE TRENCH ISOLATION METHOD USING A TWO-COMPONENT PROTECTIVE LAYER OF POLYSILICON ON SILICON NITRIDE FOR INSULATOR LAYER PLANARISATION BY CHEMICAL-MECHANICAL POLISHING
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1997/019467 International Application No.: PCT/FR1996/001844
Publication Date: 29.05.1997 International Filing Date: 21.11.1996
Chapter 2 Demand Filed: 10.06.1997
IPC:
H01L 21/3105 (2006.01) ,H01L 21/762 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105
After-treatment
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
762
Dielectric regions
Applicants:
FRANCE TELECOM [FR/FR]; 6, place d'Alleray F-75015 Paris, FR (AllExceptUS)
BROUQUET, Pierre [FR/FR]; FR (UsOnly)
MASUREL, Claude [FR/FR]; FR (UsOnly)
RIVOIRE, Maurice [FR/FR]; FR (UsOnly)
Inventors:
BROUQUET, Pierre; FR
MASUREL, Claude; FR
RIVOIRE, Maurice; FR
Agent:
BUREAU D.A. CASALONGA-JOSSE; 8, avenue Percier F-75008 Paris, FR
CASALONGA, Axel; Bureau D.A. Casalonga-Josse Morassistrasse 8 D-80469 München, DE
Priority Data:
95/1391623.11.1995FR
95/1391723.11.1995FR
Title (EN) SIDE TRENCH ISOLATION METHOD USING A TWO-COMPONENT PROTECTIVE LAYER OF POLYSILICON ON SILICON NITRIDE FOR INSULATOR LAYER PLANARISATION BY CHEMICAL-MECHANICAL POLISHING
(FR) PROCEDE D'ISOLEMENT LATERAL PAR TRANCHEES UTILISANT UNE BICOUCHE DE PROTECTION EN POLYSILICIUM SUR NITRURE DE SILICIUM POUR L'APLANISSEMENT PAR POLISSAGE MECANO-CHIMIQUE DE LA COUCHE D'ISOLANT
Abstract:
(EN) A method for isolating the working areas of a semiconductor substrate using side trenches, wherein (a) a two-component protective layer (3) consisting of silicon nitride and polysilicon is deposited on the semiconductor substrate, (b) trenches (7) are provided in the semiconductor substrate (1) alongside predetermined areas (6) of the substrate (1) that are covered with the protective layer (3) and intended to form the working areas at a later stage, (c) a layer of insulating material (8) is deposited in the trenches (7) and on the predetermined areas (6) of the substrate (1), and (d) the semiconductor block is planarised in a single step by chemical-mechanical polishing in such a way that the polysilicon of the upper layer (3b) has a higher etching rate during chemical-mechanical polishing than the insulating material, while the nitride of the lower layer (3a) has good resistance to chemical-mechanical etching. In one embodiment, the chemical-mechanical polishing of step (d) is combined with end-of-etching detection on the two-component protective layer (3).
(FR) L'invention concerne un procédé d'isolement des zones actives d'un substrat semi-conducteur par tranchées latérales qui comprend les étapes suivantes: (a) on dépose sur le substrat semi-conducteur une bicouche de protection (3) composée de nitrure de silicium et de polysilicium; (b) on réalise au sein du substrat semi-conducteur (1) des tranchées (7) disposées latéralement par rapport aux zones prédéterminées (6) du substrat (1) recouvertes de la couche de protection (3) et destinées à former ultérieurement les zones actives; (c) on dépose dans les tranchées (7) et sur les zones prédéterminées (6) du substrat (1), une couche de matériau isolant (8); et (d) on effectue un aplanissement du bloc semi-conducteur en une étape par polissage mécano-chimique de manière à ce que le polysilicium de la couche supérieure (3b) possède une vitesse d'attaque lors du polissage mécano-chimique supérieure à celle du matériau isolant, et dont le nitrure de la couche inférieure (3a) présente une bonne résistance à l'attaque physico-chimique. Selon un mode de réalisation de l'invention, on assiste de préférence le polissage mécano-chimique de l'étape (d) d'une détection de fin d'attaque s'effectuant sur la bicouche de protection (3).
Designated States: JP, US
European Patent Office (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: French (FR)
Filing Language: French (FR)