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1. (WO1997019465) METHOD IN THE MANUFACTURING OF A SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1997/019465 International Application No.: PCT/SE1996/001511
Publication Date: 29.05.1997 International Filing Date: 20.11.1996
Chapter 2 Demand Filed: 13.06.1997
IPC:
H01L 21/3213 (2006.01) ,H01L 21/331 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
321
After-treatment
3213
Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
328
Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors
33
the devices comprising three or more electrodes
331
Transistors
Applicants:
TELEFONAKTIEBOLAGET LM ERICSSON (publ) [SE/SE]; S-126 25 Stockholm, SE (AllExceptUS)
NORSTRÖM, Hans [SE/SE]; SE (UsOnly)
Inventors:
NORSTRÖM, Hans; SE
Agent:
BOHLIN, Björn ; Telefonaktiebolaget LM Ericsson Patent and Trademark Dept. S-126 25 Stockholm, SE
Priority Data:
9504150-520.11.1995SE
Title (EN) METHOD IN THE MANUFACTURING OF A SEMICONDUCTOR DEVICE
(FR) PROCEDE DE FABRICATION D'UN DISPOSITIF A SEMI-CONDUCTEUR
Abstract:
(EN) In a method of selectively etching in the fabrication of a semiconductor device, an amorphous layer (6) of said semiconductor material is deposited on a crystalline substrate (1) of the same semiconductor material. At least one dielectric layer (7) is deposited on the amorphous layer (6) such as to prevent crystallization of the amorphous layer (6). The dielectric layer (7) is preferably deposited with the aid of either a PECVD, SACVD, MBE technique or a spin-on technique. The resultant structure (1) is patterned and the dielectric layer (7) and the amorphous semiconductor layer (6) then etched away within a predetermined region (9). The method may form a sub-stage in the manufacture of a bipolar transistor having a self-registered base-emitter structure.
(FR) Dans un procédé d'attaque chimique sélective, lors de la fabrication d'un dispositif à semi-conducteur, on dépose une couche amorphe (6) d'un matériau semi-conducteur sur un substrat cristallin (1) du même matériau semi-conducteur. On dépose au moins une couche diélectrique (7) sur la couche amorphe (6) de manière à empêcher la cristallisation de cette dernière. De préférence, on dépose la couche diélectrique (7) soit à l'aide d'un procédé CVD activé au plasma, d'un procédé CVD sous pression négative, ou d'un procédé épitaxial à faisceaux moléculaires, soit à l'aide d'une technique d'application par centrifugation. On modèle la structure résultante (1) et on élimine, par attaque chimique et dans une région déterminée (9), les couches diélectrique (7) et amorphe (6). Ce procédé peut constituer une sous-étape dans la fabrication d'un transistor bipolaire présentant une structure d'émetteur-base auto-alignée.
Designated States: AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GE, HU, IL, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, TJ, TM, TR, TT, UA, UG, US, UZ, VN
African Regional Intellectual Property Organization (ARIPO) (KE, LS, MW, SD, SZ, UG)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: Swedish (SV)
Also published as:
EP0956586US6077752US6333216JP2000501234 CN1202980CA2237887
DE000069635867KR1019990067517AU1996077152