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1. (WO1997019412) IMPROVEMENTS IN OR RELATING TO REAL-TIME PIPELINE FAST FOURIER TRANSFORM PROCESSORS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1997/019412 International Application No.: PCT/SE1996/000246
Publication Date: 29.05.1997 International Filing Date: 26.02.1996
Chapter 2 Demand Filed: 11.09.1997
IPC:
G06F 17/14 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
17
Digital computing or data processing equipment or methods, specially adapted for specific functions
10
Complex mathematical operations
14
Fourier, Walsh or analogous domain transformations
Applicants:
TERACOM SVENSK RUNDRADIO [SE/SE]; Medborgarplatsen 3 S-118 92 Stockholm, SE (AllExceptUS)
HE, Shousheng [SE/SE]; SE (UsOnly)
TORKELSSON, Mats [SE/SE]; SE (UsOnly)
Inventors:
HE, Shousheng; SE
TORKELSSON, Mats; SE
Agent:
KARLSSON, Berne; Telia Research AB Rudsjöterrassen 2 S-136 80 Haninge, SE
Priority Data:
PCT/SE95/0137117.11.1995SE
Title (EN) IMPROVEMENTS IN OR RELATING TO REAL-TIME PIPELINE FAST FOURIER TRANSFORM PROCESSORS
(FR) AMELIORATIONS RELATIVES AUX PROCESSEURS PIPELINE A TRANSFORME DE FOURIER RAPIDE EN TEMPS REEL
Abstract:
(EN) A real-time pipeline processor, which is particularly suited for VLSI implementation, is based on a hardware oriented radix-22 algorithm derived by integrating a twiddle factor decomposition technique in a divide and conquer approach. The radix-22 algorithm has the same multiplicative complexity as a radix-4 algorithm, but retains the butterfly structure of a radix-2 algorithm. A single-path delay-feedback architecture is used in order to exploit the spatial regularity in the signal flow graph of the algorithm. For a length-N DFT transform, the hardware requirements of the processor proposed by the present invention is minimal on both dominant components: Log4N-1 complex multipliers, and N-1 complex data memory.
(FR) L'invention porte sur un processeur pipeline en temps réel particulièrement adapté à l'architecture VLSI et basé sur un algorithme à base 22 'orienté matériel' obtenu en intégrant une technique de décomposition en facteurs de rotation selon une approche du type division/recombinaison. L'algorithme à base 22 présente la même complexité multiplicative qu'un algorithme à base 4, mais conserve la structure en papillon d'un algorithme à base 2. On recourt à une architecture du type monovoie à rétroaction différée permettant d'exploiter la régularité spatiale du graphe de cheminement des signaux de l'algorithme. Pour une TRF de longueur N, le besoin en matériel du processeur de l'invention est minime en ce qui concerne deux composants majeurs: les multiplicateurs Log4 N-1 complexes et a mémoire de données N-1 complexes.
Designated States: CA, CN, JP, KR, NO, SG, US
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0824730US6098088CA2242823