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1. (WO1997018585) TRI-LAYER PRE-METAL INTERLAYER DIELECTRIC COMPATIBLE WITH ADVANCED CMOS TECHNOLOGIES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1997/018585 International Application No.: PCT/US1996/014340
Publication Date: 22.05.1997 International Filing Date: 05.09.1996
IPC:
H01L 21/768 (2006.01) ,H01L 23/532 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532
characterised by the materials
Applicants:
ADVANCED MICRO DEVICES, INC. [US/US]; One AMD Place Mail Stop 68 Sunnyvale, CA 94088-3453, US
Inventors:
NGO, Minh, Van; US
CHAN, Darin, A.; US
Agent:
RODDY, Richard, J.; Advanced Micro Devices, Inc. One AMD Place Mail Stop 68 Sunnyvale, CA 94088-3453, US
Priority Data:
08/559,05416.11.1995US
Title (EN) TRI-LAYER PRE-METAL INTERLAYER DIELECTRIC COMPATIBLE WITH ADVANCED CMOS TECHNOLOGIES
(FR) DIELECTRIQUE INTERCOUCHE PREMETALLIQUE A TROIS COUCHES UTILISABLE EN TECHNOLOGIE CMOS AVANCEE
Abstract:
(EN) A method of depositing a premetal dielectric layer (110) on a semiconductor substrate (102) involves depositing of a triple premetal dielectric layer (110) in in-situ deposition in a single fabrication tool with each subsequent layer being deposited after a previous layer with no intervening handling step. Thus, no intervening cleaning steps or other intermediate steps are performed; the substrate is then cleaned and chemical mechanical polished.
(FR) La présente invention concerne un procédé de dépôt d'une couche diélectrique prémétallique (110) sur un substrat de semi-conducteur (102). Ce procédé consiste à déposer in-situ une triple couche diélectrique prémétallique (110) dans un unique outil de fabrication, chaque couche ultérieure étant déposée après la couche qui la précède sans qu'il n'y ait d'opération de manipulation intermédiaire. Il en résulte qu'il n'y a aucune opération intermédiaire de nettoyage ou autre opération intermédiaire; ce n'est qu'ensuite que le substrat subit un polissage chimio-mécanique.
Designated States: JP, KR
European Patent Office (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)