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1. (WO1997017763) UNIVERSAL RECEIVER DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1997/017763 International Application No.: PCT/SE1996/001395
Publication Date: 15.05.1997 International Filing Date: 06.11.1996
Chapter 2 Demand Filed: 04.06.1997
IPC:
H03K 19/0185 (2006.01) ,H04L 25/02 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
0175
Coupling arrangements; Interface arrangements
0185
using field-effect transistors only
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
25
Baseband systems
02
Details
Applicants:
TELEFONAKTIEBOLAGET LM ERICSSON (publ) [SE/SE]; S-126 25 Stockholm, SE (AllExceptUS)
HEDBERG, Mats [SE/SE]; SE (UsOnly)
Inventors:
HEDBERG, Mats; SE
Agent:
BJELLMAN, Lennart ; Dr Ludwig Brann Patentbyrå AB P.O. Box 1344 S-751 43 Uppsala, SE
Priority Data:
9503996-210.11.1995SE
Title (EN) UNIVERSAL RECEIVER DEVICE
(FR) DISPOSITIF RECEPTEUR UNIVERSEL
Abstract:
(EN) A receiver device comprises two input circuits, connected in parallel, for receiving digital information in the form of electrical differential binary signals within a broad range of common-mode voltages. The input circuits in turn comprise transistors (14, 15, 16, 17, 24, 25) in differential input arrangements for receiving said signals. Said transistors (14, 15, 16, 17, 24, 25) of both input circuits are of one and the same type, whereby the receiver device is capable of handling higher speeds. Controlled activation and deactivation of a first one of said input circuits further enhances the speed capabilities of the receiver device.
(FR) Un dispositif récepteur comporte deux circuits d'entrée, connectés en parallèle, destinés à recevoir une information numérique sous la forme de signaux électriques binaires différentiels à l'intérieur d'une large gamme de tensions en mode commun. Les circuits d'entrée comprennent, quant à eux, des transistors (14, 15, 16, 17, 24, 25) selon une répartition d'entrée différente pour recevoir lesdits signaux. Lesdits transistors (14, 15, 16, 17, 24, 25) des deux circuits d'entrée sont d'un seul et même type et, de ce fait, le dispositif récepteur est à même de prendre en charge des vitesses plus élevées. Une activation et une désactivation commandées du premier de ces circuits d'entrée accroît, en outre, les possibilités du dispositif récepteur en matière de vitesse.
Designated States: AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GE, HU, IL, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, TJ, TM, TR, TT, UA, UG, US, UZ, VN
African Regional Intellectual Property Organization (ARIPO) (KE, LS, MW, SD, SZ, UG)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
NO19982108EP0860053US6081133JP2000503173 CN1206518CA2236785
KR1019990067387AU1996076586