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1. (WO1997017723) GaAs SUBSTRATE WITH COMPOSITIONALLY GRADED AlGaAsSb BUFFER FOR FABRICATION OF HIGH-INDIUM FETS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1997/017723 International Application No.: PCT/US1996/017956
Publication Date: 15.05.1997 International Filing Date: 08.11.1996
IPC:
H01L 21/20 (2006.01) ,H01L 29/10 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
10
with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Applicants:
LOCKHEED MARTIN CORPORATION [US/US]; 65 Spit Brook Road P.O. Box 868 Nashua, NH 03061, US
Inventors:
GILL, David, M.; US
UPPAL, Parvez, Nasir; US
Agent:
GOMES, David, W.; Lockheed Martin Corporation P.O. Box 868 Nashua, NH 03061, US
Priority Data:
08/555,02708.11.1995US
Title (EN) GaAs SUBSTRATE WITH COMPOSITIONALLY GRADED AlGaAsSb BUFFER FOR FABRICATION OF HIGH-INDIUM FETS
(FR) SUBSTRAT DE GaAs PRESENTANT UN TAMPON A COMPOSITION PROGRESSIVE DE AlGaAsSb POUR LA REALISATION DE TRANSISTORS A EFFETS DE CHAMP A FORTE TENEUR EN INDIUM
Abstract:
(EN) Semiconductor devices made in high-indium-content semiconductor material (16) have advantageous properties, but similar substrate materials are hard to handle. A buffer layer (18) makes a lattice-constant transition between a GaAs substrate and a high-indium epitaxially deposited semiconductor such as those lattice-matched to InP. The buffer layer (18) is an epitaxial layer including atoms of two Group III elements, and atoms of two Group V elements, with the ratio of the atoms of at least one group varied along the depth of the buffer layer, in a manner which makes a transition of the lattice constant between that of the substrate and the high-indium semiconductor material. The Group III elements are gallium and aluminum, and the Group V elements are arsenic and antimony.
(FR) Les dispositifs semiconducteurs réalisés dans un matériau semi-conducteur (16) à forte teneur en indium présentent des caractéristiques avantageuses mais ces matériaux, lorsqu'ils sont utilisés comme substrats, sont difficiles à manipuler. Une couche tampon (18) constitue une transition de constante de maillage entre le substrat de GaAs et le semi-conducteur produit par dépôt épitaxiale à forte teneur en indium du type de ceux présentant une correspondance de maillage avec les InP. La couche tampon (18) est une couche épitaxiale renfermant des atomes de deux éléments du Groupe III et des atomes de deux éléments du Groupe V, le rapport entre les atomes d'au moins un des groupes variant en fonction de la profondeur de la couche tampon, de sorte qu'une transition de la constante de maillage est ménagée entre celle du substrat et celle du matériau semi-conducteur à forte teneur en indium. Les éléments du Groupe III sont le gallium et l'aluminium et les éléments du Groupe V sont l'arsenic et l'antimoine.
Designated States: JP
European Patent Office (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0840942