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1. (WO1997016901) CLOCK SIGNAL CLEANING CIRCUIT
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1997/016901 International Application No.: PCT/CA1996/000706
Publication Date: 09.05.1997 International Filing Date: 24.10.1996
Chapter 2 Demand Filed: 30.05.1997
IPC:
H03K 5/1252 (2006.01) ,H04L 7/00 (2006.01) ,H04L 7/02 (2006.01) ,H04L 7/027 (2006.01) ,H04L 7/033 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
5
Manipulating pulses not covered by one of the other main groups in this subclass
125
Discriminating pulses
1252
Suppression or limitation of noise or interference
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7
Arrangements for synchronising receiver with transmitter
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7
Arrangements for synchronising receiver with transmitter
02
Speed or phase control by the received code signals, the signals containing no special synchronisation information
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7
Arrangements for synchronising receiver with transmitter
02
Speed or phase control by the received code signals, the signals containing no special synchronisation information
027
extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7
Arrangements for synchronising receiver with transmitter
02
Speed or phase control by the received code signals, the signals containing no special synchronisation information
033
using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
Applicants:
ADVANCED INTELLIGENCE INC. [CA/CA]; Suite 204-1001 Cloverdale Avenue Victoria, British Columbia V8X 4C9, CA (AllExceptUS)
ARKAS, Evan [GR/GB]; GB (UsOnly)
ARKAS, Nicholas [GR/GB]; GB (UsOnly)
Inventors:
ARKAS, Evan; GB
ARKAS, Nicholas; GB
Agent:
SMITH, Dallas ; Gowling, Strathy & Henderson Suite 2600 160 Elgin Street Ottawa, Ontario K1P 1C3, CA
SECHLEY, Konrad, A.; Gowling, Strathy & Henderson Suite 2600 160 Elgin Street Ottawa, Ontario K1P 1C3, CA
Priority Data:
2,161,98202.11.1995CA
Title (EN) CLOCK SIGNAL CLEANING CIRCUIT
(FR) CIRCUIT D'EPURATION DE SIGNAUX D'HORLOGE
Abstract:
(EN) A device which reduces jitter and narrows the frequency spectrum of a jitter-ridden clock signal includes a basic unit having a plurality of series connected delay elements outputs from each delay element are all connected to an AND/NAND gate. A front end of the device locates missing clock pulses and ensures regular clock pulses are relayed to the remainder of the device. A succeeding section including plural basic units hones the signal such that jitter elements are removed. By the output of this section time duty cycles are uneven, a positive edge triggered flip-flop is then used to obtain 50 % duty cycles at the expense of halving the clock signal's frequency. Optionally a frequency doubler can be employed to regain the clock signal's original frequency.
(FR) Un dispositif qui diminue les sautillements et réduit de spectre de fréquence d'un signal d'horloge affecté de sautillements comprend une unité de base présentant une pluralité de sorties d'éléments de temporisation reliées chacune en série depuis chaque élément de temporisation à une porte ET/NON-ET. Une extrémité avant du dispositif localise les impulsions d'horloge manquantes et s'assure de ce que des impulsions d'horloge régulières sont transmises au restant du dispositif. Une section suivante comprenant plusieurs unités de base affine le signal jusqu'à l'élimination des sautillements. A la sortie de cette section, les cycles de marche sont irréguliers dans le temps et on utilise un flip-flop positif déclenché par un front pour obtenir des facteurs de marche de 50 %, cela au détriment d'une division par deux de la fréquence du signal d'horloge. On peut utiliser un doubleur de fréquence pour revenir à la fréquence d'origine du signal d'horloge.
Designated States: CA, JP, US
European Patent Office (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0858699US6246276CA2236423