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1. (WO1997016853) INSULATED GATE SEMICONDUCTOR DEVICES WITH IMPLANTS FOR IMPROVED RUGGEDNESS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1997/016853 International Application No.: PCT/US1995/014294
Publication Date: 09.05.1997 International Filing Date: 02.11.1995
IPC:
H01L 29/06 (2006.01) ,H01L 29/10 (2006.01) ,H01L 29/74 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
10
with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70
Bipolar devices
74
Thyristor-type devices, e.g. having four-zone regenerative action
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
NATIONAL SEMICONDUCTOR CORPORATION [US/US]; 1090 Kifer Road M/S 16-135 Sunnyvale, CA 94086-3737, US
Inventors:
BULUCEA, Constantin; US
BLANCHAR, Richard, A.; US
Agent:
CONSER, Eugene; National Semiconductor Corporation 1090 Kifer Road M/S 16-135 Sunnyvale, CA 94086-3737, US
Priority Data:
Title (EN) INSULATED GATE SEMICONDUCTOR DEVICES WITH IMPLANTS FOR IMPROVED RUGGEDNESS
(FR) DISPOSITIFS A SEMI-CONDUCTEURS A GRILLE ISOLEE AVEC IMPLANTS CONFERANT PLUS DE ROBUSTESSE
Abstract:
(EN) Vertical planar and non-planar insulated gate semiconductor device cells having improved ruggedness under drain avalanche conditions are disclosed. The cells employ high concentration implants which are strategically located in the central cell regions. The implants are effective to concentrate the electric field intensity and avalanche current flow in the central cell region and to prevent current flow into the base of a parasitic bipolar transistor, thereby preventing activation of the transistor. Both surface-peaked and subsurface-peaked implants are disclosed.
(FR) La présente invention a pour objet des cellules de dispositifs à semi-conducteurs à grille isolée de type planar et non planar, dont la robustesse est améliorée en régime d'avalanche de drains. Les cellules utilisent des implants à concentration élevée qui sont situés de façon stratégique dans des régions centrales de cellules. Les implants servent à concentrer l'intensité de champ électrique et la circulation du courant en avalanche dans la région centrale de cellules, ainsi qu'à empêcher la circulation du courant dans la base d'un transistor bipolaire parasite, ce qui a pour effet d'empêcher l'activation du transistor. La présente invention concerne à la fois les implants superficiels en crête et les implants en crête en dessous de la surface.
Designated States: DE, KR
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0801817DE000069530517KR1019987001137