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1. (WO1997016830) TEMPERATURE COMPENSATED REFERENCE FOR OVERERASE CORRECTION CIRCUITRY IN A FLASH MEMORY
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1997/016830 International Application No.: PCT/US1996/012020
Publication Date: 09.05.1997 International Filing Date: 19.07.1996
Chapter 2 Demand Filed: 01.04.1997
IPC:
G11C 16/28 (2006.01) ,G11C 16/34 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
26
Sensing or reading circuits; Data output circuits
28
using differential sensing or reference cells, e.g. dummy cells
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
34
Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
Applicants:
ADVANCED MICRO DEVICES, INC. [US/US]; One AMD Place Mail Stop 68 Sunnyvale, CA 94088-3453, US
Inventors:
CLEVELAND, Lee, E.; US
CHEN, Johnny, C.; US
Agent:
PITRUZZELLA, Vincenzo, D.; Advanced Micro Devices, Inc. Mail Stop 68 One AMD Place Sunnyvale, CA 94088-3453, US
BROOKES & MARTIN; "Association No. 14" High Holborn House 52/54 High Holborn London WC1V 6SE, GB
Priority Data:
08/551,42201.11.1995US
Title (EN) TEMPERATURE COMPENSATED REFERENCE FOR OVERERASE CORRECTION CIRCUITRY IN A FLASH MEMORY
(FR) REFERENCE COMPENSEE PAR LA TEMPERATURE DESTINEE A UN CIRCUIT DE CORRECTION DU SUREFFACEMENT DANS UNE MEMOIRE FLASH
Abstract:
(EN) A reference circuit for overerase correction in a flash memory includes a reference flash memory cell biased in a substantially similar manner to that of an overerased flash memory cell. The leakage current for the reference flash memory cell is preset to a tolerable level of leakage current for a maximum operating temperature of the flash memory and the reference flash memory cell tracks the temperature characteristics of the overerased flash memory cell, to avoid costly overcorrection at high temperatures.
(FR) Ce circuit de référence pour la correction du sureffacement dans une mémoire flash comprend une cellule de mémoire flash de référence orientée sensiblement de la même manière qu'une cellule de mémoire flash sureffacée. Le courant de fuite pour la cellule de mémoire flash de référence est établi à l'avance à un niveau tolérable de courant de fuite pour une température de fonctionnement maximale de la mémoire flash, la cellule de mémoire flash de référence surveillant les caractéristiques de température de la cellule de mémoire flash sureffacée pour empêcher la surcorrection coûteuse à des températures élevées.
Designated States: JP, KR
European Patent Office (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0858660