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1. (WO1997016742) CONDITIONALLY GENERATING TEST INSTRUCTIONS DEPENDING ON DEVICE DEFECT DATA
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1997/016742 International Application No.: PCT/US1996/017423
Publication Date: 09.05.1997 International Filing Date: 30.10.1996
Chapter 2 Demand Filed: 02.06.1997
IPC:
G01R 31/28 (2006.01) ,G01R 31/3183 (2006.01) ,G01R 31/319 (2006.01) ,G06F 11/25 (2006.01)
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28
Testing of electronic circuits, e.g. by signal tracer
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28
Testing of electronic circuits, e.g. by signal tracer
317
Testing of digital circuits
3181
Functional testing
3183
Generation of test inputs, e.g. test vectors, patterns or sequences
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28
Testing of electronic circuits, e.g. by signal tracer
317
Testing of digital circuits
3181
Functional testing
319
Tester hardware, i.e. output processing circuits
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
22
Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
25
Testing of logic operation, e.g. by logic analysers
Applicants:
GENRAD, INC. [US/US]; 300 Baker Avenue Concord, MA 01742, US
Inventors:
BLUMENAU, Steven, M.; US
SCHYMIK, William, S.; US
PYE, Richard; US
KEATING, Paul, L.; US
Agent:
BORN, Joseph, H.; Cesari and McKenna, L.L.P. 30 Rowes Wharf Boston, MA 02110, US
Priority Data:
08/551,95302.11.1995US
Title (EN) CONDITIONALLY GENERATING TEST INSTRUCTIONS DEPENDING ON DEVICE DEFECT DATA
(FR) ELABORATION CONDITIONNELLE D'INSTRUCTIONS D'ESSAI EN FONCTION DES STATISTIQUES DE DEFECTUOSITES DE COMPOSANTS
Abstract:
(EN) A system for generating test programs while inhibiting unnecessary testing of devices. The system includes a database of defect statistics (2105) organized by package type. The system generates a test program (5100) by following, for each part on the circuit board, a rule for each type of test instruction (3120). Each rule may have an expression dictating whether the corresponding type of instruction should be generated for a certain circuit board part. Each expression may have a variable called DPM, which is a defect statistic corresponding to the package type of the part. Thus the system conditionally generates a test instruction for a part depending on whether the package type of the part has a defect statistic above a certain threshold.
(FR) L'invention porte sur un système d'élaboration de programmes d'essai permettant de se passer de dispositifs d'essai non nécessaires et comportant une base de données de statistiques de défectuosités (2105) organisée par type de groupements. Pour l'élaboration d'un programme d'essai (5100), le système suit pour chacune des parties du circuit imprimé une règle propre à chacun des types d'instructions d'essai (3120). Chacune de ces règles peut comporter une indication précisant si le type correspondant d'instruction doit être élaboré pour une portion donnée du circuit. Chacune des indications peut comprendre une variable dite DPM qui représente la statistique de défectuosité correspondant au type de groupement auquel appartient la pièce. Le système peut ainsi élaborer conditionnellement une instruction d'essai pour une pièce selon que le type de paquet de la pièce présente ou non une statistique de défectuosité dépassant un certain seuil.
Designated States: JP
European Patent Office (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)