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1. (WO1997015980) TRANSMITTER COMPRISING CARRIER SUPPRESSION AND DC OFFSET REDUCTION MEANS
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CLAIMS

1 . A transmitter comprising frequency up-converting means for frequency up-converting an input signal to a transmission frequency, power amplifying means coupled to the frequency up-converting means, a feedback loop including means for deriving a portion of the amplitude of the output of the power amplifying means, frequency down-converting means for frequency down-converting the derived portion of the output of the power amplifying means, means for determining the dc offset at the input of the frequency up-converting means, means for subtracting the dc offset from the linearisation loop feedback error signal and for applying the difference signal obtained to the frequency up-converting means.

2. A transmitter as claimed in Claim 1 , characterised in that the means of determining the dc offset comprises sampling means having an input coupled to an input of the frequency up-converting means and an output coupled to the subtracting means, said sampling means having means for storing a dc offset voltage sampled at the input of the frequency upconverting means, and in that switching means is provided in a signal path of the signal at the transmission frequency in order to reduce the amplitude of said signal to zero whilst the dc offset voltage is being sampled.

3. A transmitter as claimed in Claim 2, characterised in that the sampling means comprises further switching means coupled to dc offset storage means, and in that said switching means and said further switching means operate in anti-phase to each other.

4. A transmitter as claimed in Claim 1 , 2 or 3, characterised in that the subtracting means comprises first and second differencing means each having first and second inputs and an output, in that the first input of the first differencing means is coupled to receive the input signal, the second input is coupled to the output of the second differencing means and its output is coupled to the frequency up-converting means and in that the second differencing means comprises amplifying means, the first input of which is coupled to the frequency up-converting means, the second input of which is coupled to the output of the frequency down-converting means and the output of which is coupled to the second input of the first differencing means.

5. A transmitter comprising at least first and second phase related signal paths, each of the first and second paths including frequency upconverting means for frequency up-converting respective input signals to a transmission frequency, means for combining outputs of the respective frequency up-converting means, power amplifying means coupled to the combining means, a feedback loop including means for deriving a portion of the output of the power amplifying means, signal splitting means for dividing the signal derived from the power amplifying means into at least first and second phase related feedback paths, each of the first and second phase related feedback paths comprising frequency down-converting means for frequency down-converting its portion of the derived signal at the transmission frequency, means for determining the dc offsets at the inputs of the respective frequency up-converting means and means for subtracting the respective dc offset from the respective linearisation loop feedback error signal and for applying the difference signal obtained to the respective frequency up-converting means.

6. A transmitter as claimed in Claim 5, characterised in that the means of determining the dc offsets comprises respective sampling means, each said sampling means having an input coupled to an input of the respective frequency up-converting means and an output coupled to its respective subtracting means, in that each said sampling means has means for storing a dc offset voltage sampled at the input of its respective frequency up-converting means, and in that switching means is provided in a signal path of the signal at the transmission frequency in order to reduce the amplitude of said signal to zero whilst the dc offset voltage is being sampled.

7. A transmitter as claimed in Claim 6, characterised in that the respective sampling means each comprise further switching means coupled to the dc offset voltage storing means, and in that said switching means and said further switching means operate in anti-phase to each other.

8. A transmitter as claimed in Claim 5, 6 or 7, characterised in that the respective subtracting means comprise first and second differencing means each having first and second inputs and an output, in that the first input of the first differencing means is coupled to receive its respective input signal, the second input is coupled to the output of the second differencing means and its output is coupled to its respective frequency up-converting means and in that the second differencing means comprises amplifying means, the first input of which is coupled to its respective frequency upconverting means, the second input of which is coupled to the output of its respective frequency down-converting means and the output of which is coupled to the second input of the first differencing means.

9. A transmitter as claimed in Claim 3 or 6, characterised in that the dc offset voltage storing means comprises analogue voltage storage means.

10. A transmitter as claimed in Claim 3 or 6, characterised in that the dc offset voltage storing means comprises digital storage means.