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1. (WO1997015950) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1997/015950 International Application No.: PCT/JP1996/002686
Publication Date: 01.05.1997 International Filing Date: 18.09.1996
Chapter 2 Demand Filed: 29.10.1996
IPC:
H01L 27/108 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
Applicants:
HITACHI, LTD. [JP/JP]; 6, Kanda Surugadai 4-chome Chiyoda-ku Tokyo 101, JP (AllExceptUS)
FUKUDA, Takuya [JP/JP]; JP (UsOnly)
KOBAYASHI, Nobuyoshi [JP/JP]; JP (UsOnly)
NAKAMURA, Yoshitaka [JP/JP]; JP (UsOnly)
SAITO, Masayoshi [JP/JP]; JP (UsOnly)
FUKADA, Shinichi [JP/JP]; JP (UsOnly)
KAWAMOTO, Yoshifumi [JP/JP]; JP (UsOnly)
Inventors:
FUKUDA, Takuya; JP
KOBAYASHI, Nobuyoshi; JP
NAKAMURA, Yoshitaka; JP
SAITO, Masayoshi; JP
FUKADA, Shinichi; JP
KAWAMOTO, Yoshifumi; JP
Agent:
USUDA, Toshiyuki; Sun Crest Building, 4th floor 3-16, Hon-cho 4-chome Kokubunji-shi Tokyo 185, JP
Priority Data:
7/28095727.10.1995JP
Title (EN) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME
(FR) DISPOSITIF A CIRCUIT INTEGRE A SEMI-CONDUCTEUR ET SON PROCEDE DE FABRICATION
Abstract:
(EN) A novel memory cell structure due to which the problem of the step is avoided without increasing the number of processes and a device structure due to which common part in manufacturing processes of the same substrate are increased and countermeasures can be taken against environmental problems without increasing the number of processes. In the memory cell structure, a capacitor is formed in the uppermost layer of a plurality of metal wiring layers by connecting the storage node of the capacitor to a diffusion layer with a plug and a pad. It is desirable to connect an auxiliary capacitor composed of a dielectric film formed in at least one of the metal interconnection layers below the uppermost layer, a storage node, and plate electrodes to the capacitor. It is also desirable to cover a chip with the plate electrodes of the capacitor.
(FR) L'invention porte sur une nouvelle structure de cellule de mémoire permettant d'éviter le problème d'étape de traitement sans avoir à multiplier le nombre de processus et sur une structure de dispositif permettant d'accroître la partie commune des processus de fabrication et de prendre des contre-mesures à l'encontre de problèmes d'environnement sans avoir non plus à multiplier le nombre de processus. On monte, dans cette structure de cellule de mémoire, un condensateur sur la couche la plus élevée de plusieurs couches métalliques de câblage en connectant le noeud de stockage du condensateur à une couche de diffusion à l'aide d'une fiche ou d'une plage de connexion. Il est préférable de connecter un condensateur auxiliaire composé d'une pellicule diélectrique formée dans l'une au moins des couches métalliques d'interconnexion sous la couche la plus élevée, un noeud de stockage ainsi que des électrodes à plaque au condensateur. Il est également préférable de recouvrir une microplaquette par les électrodes à plaque du condensateur.
Designated States: KR, US
European Patent Office (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
US6432769US6479899US20020195641KR1019990067022